PDA-NFL pressure sensor chip was designed using both results obtained from an analytical mathematical model and from software modeling. Both lateral p-n-p type (L-PNP) and vertical n-p-n type (V-NPN) BJTs located on the membrane and on the frame (sensitive / not sensitive to pressure) were analyzed and included in the designs. Electrical circuit with NPN transistors used in the sensor chip is shown in Fig. 1a. Values of PRs and operating point of BJTs providing good balance between sensitivity and temperature compensation were determined analytically. Sentaurus TCAD software was used to finalize technological details. A process flow where all PRs, base of V-NPN BJT, emitter and collector of L-PNP BJT are created in one process step by diffusion of boron (p-) was chosen. The p- layer has surface concentration NS = 6∙1018 cm-3 (sheet resistance 200 Ohm/sq., p-n junction depth 2.2 μm). This allows for making PRs with high sensitivity to stress (piezoresistive coefficient π44 = 1,26∙10-9 Pa-1 for [110] direction). Phosphorous doping (n+) and drive-in were selected based on the target parameters of transistors. V-NPN BJT was designed to have gain βV-NPN = 150, base current Ib V-NPN = 5 μА and collector-base voltage drop of 0.80 V. L-PNP BJT had target gain βL-PNP = 5, base current Ib L-PNP = 50 μА; and collector-base voltage drop of 0.86 V (Fig. 2). All parameters of electrical circuit PDA-NFL presented in Table I. Four pairs of PRs placed in the areas with high mechanical stress (MS) selected with help of modeling in ANSYS (Fig. 3b). The target values of PRs were obtained by changing their length, while width of all eight PS was chosen to be 10 μm. P- regions of PRs formed on the thin part of the membrane connected to metal lines on the frame by P+ areas. The chip uses Al-Si (1.5% Si) metallization. The PR resistances change as shown on Fig. 1a in response to applied pressure.
Pressure sensor chips were manufactured using (100) p-type Si wafers with n-type epitaxial layer. Required isolation of the BJTs was achieved by deep diffusion of p+ regions. The dimensions of pressure sensor chip with PDA-NFL are 4.0×4.0×0.4 mm3. It has square membrane with three rigid islands (RIs) formed by anisotropic wet etching in KOH (Fig. 3a and Table II). Sensors for three different pressure ranges: 60 kPa, 5 kPa and 1 kPa have been manufactured.
Table I. Parameters of PDA-NFL circuit.
Parameters
|
V-NPN circuit
|
L-PNP circuit
|
|
Analytical
|
Multisim
|
Analytical
|
Multisim
|
Base current BJT Ib, μА
|
5.0
|
4.6
|
50.0
|
44.0
|
Gain BJT β
|
150
|
145
|
5
|
5
|
Base-emitter voltage drop BJT (Ub – Uem), V
|
0.80
|
0.80
|
0.78
|
0.77
|
Collector-base voltage drop BJT (Uc –Ub), V
|
0.81
|
0.80
|
0.86
|
0.86
|
Collector potential BJT Uc, V
|
2.50
|
2.79
|
2.50
|
2.81
|
Parasitic current to substrate BJT Ipar, μА
|
-
|
33.0
|
Rb11, B21, kOhm
|
4.47
|
3.00
|
Rb12, B22, kOhm
|
2.98
|
2.00
|
Rc1, c2, kOhm
|
3.33
|
10.00
|
Rem1, em2, kOhm
|
1.79
|
1.50
|
Table II. Geometrical parameters of pressure sensor chip PDA-NFL for 60, 5 and 1 kPa.
Geometrical Parameter (Fig. 3a)
|
Size, μm
|
Pressure sensor chip PDA-NFL
|
60 kPa
|
5 kPa
|
1 kPa
|
L
|
4000 ± 20
|
H
|
400 ± 5
|
A
|
2260 ± 20
|
W
|
33 ± 2
|
9 ± 2
|
D
|
41 ± 5
|
23 ± 5
|
39 ± 5
|
Z
|
490 ± 50
|
790 ± 50
|
270 ± 50
|
NI Multisim software was used for evaluation of chip sensitivity and additional temperature error based on the design parameters. Some results are shown in Fig. 4. Comparison of pressure sensitivity of the circuits with BJT sensitive / not sensitive to pressure shows that stress-sensitive BJTs placed on the membrane can increase pressure sensitivity only by about 1-5 % [30-32].
Placing BJTs on the frame has some advantages: it allows for achieving more symmetrical layout of components and avoiding connections between active and passive components on the membrane. Pressure sensor chip PDA-NFL with BJTs located on the membrane (pressure-sensitive) was fabricated but did not function properly due to a mistake in layout.
Theoretical model shows that electrical circuit PDA-NFL with V-NPN BJT is better than electrical circuit PDA-NFL with L-PNP BJT, for example for 60 kPa range: sensitivity SV-NPN = 1.736 mV/V/kPa and SL-PNP = 1.402 mV/V/kPa, additional temperature error for zero signal TCZV-NPN = 0.026 %FS/°С and TCZL-PNP = 0.584 %FS/°С. Parasitic current from emitter to substrate should be taken into account in the circuit utilizing L-PNP BJT (see Table II). This current exists even when p-n junction between epitaxial layer and substrate is closed. Analysis by TCAD shows that 67% of transistor current goes to the substrate. This fact has been confirmed experimentally. Therefore, section III contains only test data for pressure sensor chip PDA-NFL with V-NPN BJT located on the frame and not sensitive to pressure.