Scalable and CMOS compatible hardware authentication using silicon photonic physical unclonable functions

doi:10.21203/rs.3.rs-1686290/v1

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Scalable and CMOS compatible hardware authentication using silicon photonic physical unclonable functions

https://doi.org/10.21203/rs.3.rs-1686290/v1

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We demonstrate the uniqueness, unclonability and secure authentication of N = 56 physical unclonable functions (PUFs) realized from silicon photonic moiré quasicrystal interferometers (QCIs). Compared to prior photonic-PUF demonstrations typically limited in scale to only a handful of unique devices and on the order of 10 false authentication attempts, this work examines > 10³ inter-device comparisons and false authentication attempts. Device fabrication is divided across two separate fabrication facilities, allowing for cross-fab analysis and emulation of a malicious foundry with exact knowledge of the PUF photonic circuit design and process. Our analysis also compares cross-correlation based authentication to the traditional Hamming distance method and experimentally demonstrates an authentication error rate AER = 0%, false authentication rate FAR = 0%, and an estimated probability of cloning (POC) below 10^− 30. This work validates the potential scalability of integrated photonic-PUFs which can attractively leverage mature wafer-scale manufacturing and automated contact-free optical probing. Such structures show promise for authenticating hardware in the untrusted supply chain or augmenting conventional electronic-PUFs to enhance system security.

Physical unclonable functions (PUFs) have garnered significant attention within the micro-electronics and hardware security communities due to their ability to provide chip-unique signatures which provide a foundation for performing many cryptographic applications^1–3. As electronic-PUFs have continued to mature⁴, their prospective limitations and vulnerabilities have become increasingly important factors to address and/or circumnavigate. Along this vein, photonic-PUFs have witnessed renewed and increasing interests in recent years as they attractively offer an inherently non-electronic platform with rich underlying physics and large information capacity.

A variety of photonic-PUFs have now been demonstrated across both classical ^5–8 and quantum regimes ^9,10, ranging from purely passive devices ^6–8 to active non-linear devices^11,12. Photonic-PUFs are also uniquely compatible with non-contact optical probing as well as optical communication links^11,13, allowing them to provide increasingly distinct functionalities. These and future iterations of photonic-PUFs are expected to facilitate cryptographic applications such as secure authentication, identification, and communication through a variety of device formats, i.e., passive/active, all-optical, electronic-photonic, and quantum-optical. Moreover, with the recent maturation and successful commercialization of integrated silicon photonics, a variety of photonic-PUFs can now be scalably realized in modern complementary metal–oxide–semiconductor (CMOS) fabrication processes. However, most photonic-PUFs reported to date have been realized and studied in very limited quantities, i.e., ranging from only a few devices^5,8 up to roughly one dozen¹². As photonic-PUFs push from proof-of-concept devices toward practical and scalable security solutions, it is increasingly important to examine and validate their characteristics on larger scales.

In our prior work, we have demonstrated a proof-of-concept photonic-PUF based on a silicon photonic moiré quasicrystal interferometer (QCI) which was instantiated N = 3 times ⁸. This replication allowed for N = 3 unique device authentications and M = N(N - 1) = 6 inter-device comparisons or false authentication attempts. In this report, we further extend our research to a substantial N = 56 device instantiations realized in batches of 28 devices across two different fabrication facilities, with each instantiation and fab utilizing an exact copy of the same underlying QCI design. Semi-automated PUF measurements followed by digital key extraction enable N = 56 unique authentications and M = N(N-1) = 3,080 inter-device comparisons or false authentication attempts to be performed. These photonic-PUF characterizations enable estimation of the authentication error rate (AER), false authentication rate (FAR), and probability of cloning (POC) as a function of the analysis parameters and/or authentication technique (e.g. Hamming vs. correlation based). Our results provide strong evidence of device uniqueness and unclonability and highlight disordered integrated photonics as a promising and scalable paradigm for realizing hardware security solutions.

Approach

Figure 1 illustrates our QCI based PUF and secure authentication framework. The QCI design is described in detail in Ref. ⁸. Briefly, within each arm of the interferometer are waveguide spirals that contain identically designed silicon photonic quasicrystals which lack translational symmetry and support Aubry-André analyticity breaking¹⁴ and a 1D localization/delocalization transition¹⁵. The randomized nature of each photonic-PUF’s transmission spectrum is derived the QCI design being highly sensitized to distributed fabrication induced imperfections, such as nanoscale errors in waveguide width, which modulate the effective index profile of each quasicrystal and can induce transitions from delocalized waveguiding to localized resonant behavior. By designing our structures to include regions with narrow grating teeth and a small sidewall modulation depth of +/- 20nm, we intentionally maximize the relative impact that nanoscale imperfections and natural spatially distributed fabrication disorder impart onto the realized devices¹⁶. Meanwhile, the grating couplers and single-mode waveguides act as polarization and mode filters which ensure the PUF response is insensitive to drifts or variations in probing conditions (e.g. polarization, angular or spatial alignment). In addition to enabling compact footprint and CMOS compatibility, the integrated nature of the device provides inherent robustness or reliability advantages over free-space or fiber based optical PUFs which may be highly sensitized to probing or environmental conditions⁸.

In this work, half, or N//2 = 28, of the identically designed PUF devices, were co-fabricated in two separate fabrication runs at (1) University of Washington Nanofabrication Facility and (2) Applied Nanotools fabrication facility, referred to here as “Fab 1” and “Fab 2” respectively (see Methods). As illustrated in Figure 1, a digital key is extracted from each photonic-PUF through a series of steps. First, the device transmission spectra are collected with a tunable laser (Agilent 81600B) with a 10 pm resolution. The slowly varying spectral envelope associated with the grating couplers is then removed using a polynomial baseline correction. Note: spectra for all 56 devices are available in the supplementary information Fig. S1. The spectral features remaining after baseline correction are then purely associated with the photonic-PUF under test. The spectra are then binarized in gray code by rescaling the log scale transmission loss into a range between 0 and 2^k-1, where k is the number of bits for binarization. We then remove the most significant bit (MSB) so that the bit length per sample is k - 1. The total bit length L of each photonic-PUF derived key is then L = K(k - 1) where K is the number of wavelength samples. In our case, a 35 nm spectral wavelength window (1540 nm – 1575 nm) with a resolution of 10 pm results in K = 3500 and choosing k = 3 produces a key length of L = 7000 bits for each PUF.

To investigate device authentication all devices were remeasured approximately two days after their initial room temperature measurement at a secondary temperature (30^oC). A subset of the binary keys extracted for all 56 PUFs for k = 3 at 25^oC and 30^oC are visualized in Fig. 2a & 2b respectively. Due to silicon’s thermo-optic effect shifting the spectral response of each device in the wavelength domain over temperature, a corresponding shift in the bit sequence of each key is also observed. Experimentally we observe a shift of 70 bits (Fig. 2) indicating a thermo-optic wavelength shift of ~ 35 pm, which is in close agreement with prediction based on silicon’s thermo-optic coefficient of 1.86 x 10^− 4 RIU/K¹⁷ and a waveguide transverse confinement factor in silicon near ~ 0.88.

To evaluate authenticity or uniqueness between an enrolled key x(n) from the database and a new test key y(n), we measure the similarity between the two keys while simultaneously mitigating the influence of thermo-optic effects. Previously we have reported one analysis approach based on a “sliding key” Hamming distance (HD) computation, wherein the fractional HD is computed while shifting the test key relative to the enrolled key, with the output HD reported as the minimum fractional HD value obtained across all key lags⁸. A second and more standardized approach, evaluated here, would be to simply compute the normalized cross-correlation between the enrolled key, x(n), and the test key, y(n), and to record the maximum normalized cross-correlation value ${C}_{xy}$ according to¹⁸:

$${C}_{xy}=\text{max}\left\{\frac{{R}_{xy}\left(m\right)}{\sqrt{{R}_{xx}\left(0\right){R}_{yy}\left(0\right)}}\right\}$$

where the unnormalized cross-correlation ${R}_{xy}\left(m\right)$ as a function of lag m is defined according to:

$${R}_{xy}\left(m\right)=\left\{\begin{array}{c}\sum _{n=1}^{L-m}x(n+m\left)y\right(n), m\ge 0\\ \sum _{n=1}^{L+m}y(n-m\left)x\right(n), m<0\end{array}\right.$$

Unlike a single HD or correlation computation, this cross-correlation based analysis naturally mitigates for any bit shifts that arise from the thermo-optic drift of the PUF’s spectral signature.

Figures 2c & 2d illustrate the cross-correlation results for selected PUFs and confirm that distinct PUF keys are both uncorrelated and aperiodic. To facilitate arithmetic computation of the cross-correlation from a logical bit sequence, we assign logical ‘1’ to a positive variable a and logical ‘0’ to its negative, -a. For an ideally unbiased sequence with equiprobability of ‘0’ or ‘1’, this approach naturally removes the DC component of the signals. Note: a resulting correlation value C_xy near 1 or -1 indicates strong correlation or anti-correlation respectively, while C_xy near 0 indicates signals that are uncorrelated. The aperiodic vs. periodic nature of a given key is evaluated by identifying either only one spike or multiple spikes respectively from the cross-correlation or cross-autocorrelation.

Next, we expand our analysis to all 56 PUFs and test for device authenticity by enrolling each key measured at 25^oC and comparing against all 56 test keys measured at 30^oC, allowing us to examine N = 56 ‘intra-chip’ authentication attempts and N(N-1) = 3080 ‘inter-chip’ false authentication attempts. To explore potential trade-offs between PUF key size and the reliability of each analysis technique (e.g. HD or correlation), we examined results for k values from 2 to 5 resulting in key sizes ranging from L = 1750 to 14,000 (supplementary Figure S2). A summary of the correlation and HD based authentication results for k = 3 and 5 are reported in Fig. 3. As shown in Figs. 3a & 3b, the cross-correlation technique effectively distinguishes between fake and authentic devices for both key lengths as the inter-chip and intra-chip distributions are well isolated. For example, a correlation decision threshold near ~ 0.25 could be used to confidently distinguish between authentic vs. fake devices with an experimentally observed false authentication rate (FAR) of 0% and authentication error rate (AER) of 0%. The HD technique also works effectively for k = 3, but exhibits a degradation in AER performance for k = 5 as indicated in Figs. 3c & 3d. These results suggest the HD method is more sensitive than the cross-correlation to bit errors which increase as the PUF spectra are digitized with higher resolution.

From the measured inter-chip and intra-chip probability density functions (pdfs), we then estimate the probabilities of false authentication (FA) and authentication error (AE) as a function of the decision threshold by computing the corresponding cumulative distribution functions (cdf) as reported in Figures 3e & 3f. The probability of false authentication effectively provides an estimate of the PUF cloning probability. In the case where our PUF keys are authenticated using cross-correlation with k = 3 and 5, a decision threshold of 0.25 corresponds to estimated POC values below 10^-30 and 10^-40 respectively. The HD based analysis indicates a similar degree of unclonability, which suggests the primary benefits of the cross-correlation technique are its straightforward implementation, computational efficiency¹⁸, and improved intra-chip reliability, particularly for larger k.

Lastly, we summarize and breakdown our results according to the originating fabrication facility, with PUFs 1–28 corresponding to ‘Fab 1’ and PUFs 29–56 corresponding to ‘Fab 2’. As indicated by inspecting QCI PUF spectra from each fab (Fig. 4a and Supplementary Fig. S1), all QCIs provide randomized spectral features in the same working spectral window with similar extinction ratios. This indicates the processes are approximately matched in terms of propagation loss and the nominal waveguide dimensions which affect the nominal effective index and Bragg wavelengths of the constituent moiré sub-lattices used to construct the QCI. The results also qualitatively suggest a similar degree of nanoscale fabrication induced disorder is naturally present in each process. Despite these similarities, we found all 56 PUFs to be unique and uncorrelated to one-another as noted in results from Fig. 3 and summarized in Fig. 4b. Moreover, the uncorrelated nature of each distinct PUF is not found to exhibit any dependence on the fabrication facility, as the mean inter-chip correlation coefficient (maximum cross-correlation) is unchanged when comparing devices from the same fab (µ = 0.07) vs. comparing devices across fabs (µ = 0.07) as shown in Fig. 4c. In other words, devices from both fabs were measured to be equally unclonable. The mean intra-chip correlation coefficient, however, does exhibit a small dependence on the fabrication facility, with devices originating from Fab 1 being authenticated with a higher mean correlation coefficient (µ = 0.78) than devices originating from Fab 2 (µ = 0.74). This however does not impact the empirically measured AER, which is observed to be 0% for devices from each fabrication facility.

Our findings support the conclusion that QCI based silicon photonic-PUFs are a scalable solution for secure authentication in the untrusted supply chain. Compared to prior works typically comparing on the order of 10 inter-chip PUF signatures, this work compares > 10³ inter-chip PUF signatures. We observe zero authentication errors (out of N = 56 attempts) and zero false authentications (out of M = 3,088 attempts). These results are achieved from devices replicated from the exact same PUF photonic circuit design across two different fabrication facilities. The size of this dataset allows us to empirically test the unclonability of our photonic-PUFs and to estimate the probability of cloning at less than 10^− 30. As such, this work provides an important step toward scalable implementation of photonic-PUFs in practical hardware authentication applications. These photonic-PUFs are also attractive for chip identification applications since they provide chip-unique signatures which could be used to identify and track parts from front-end wafer processing through to packaging and/or deployment within the untrusted supply chain, effectively serving as unforgeable and tamper-proof lot, wafer, and/or die identifiers. Furthermore, we anticipate related types of photonic-PUF structures, based on integrated photonics, can be scalably employed in active optoelectronic, all-optical, or quantum readout schemes to facilitate applications such as remote authentication and secure communication.

Device fabrication and testing. For this work, device fabrication and measurement was performed through the edX UBCx Phot1x Silicon Photonics Design, Fabrication and Data Analysis course (organized by L. Chrostowski)¹⁹. Half, or N/2 = 28, of the identically designed PUF devices were co-fabricated in two separate fabrication runs at the University of Washington nanofabrication facility (WNF or ‘Fab 1’) and Applied Nanotools (ANT or ‘Fab 2’) fabrication facility. Applied Nanotools, Inc. NanoSOI process: The NanoSOI MPW fabrication process by Applied Nanotools Inc. (http://www.appliednt.com/nanosoi; Edmonton, Canada) is based on direct-write 100 keV electron beam lithography technology. Silicon-on-insulator wafers of 200 mm diameter, 220 nm device thickness and 2 µm buffer oxide thickness are used as the base material for the fabrication. After an initial wafer clean using piranha solution (3:1 H₂SO₄:H₂O₂) for 15 minutes and water/IPA rinse, hydrogen silsesquioxane (HSQ) resist was spin-coated onto the substrate and heated to evaporate the solvent. The photonic devices were patterned using a Raith EBPG 5000 + electron beam instrument using a raster step size of 5 nm. The exposure dosage of the design was corrected for proximity effects that result from the backscatter of electrons from exposure of nearby features. Shape writing order was optimized for efficient patterning and minimal beam drift. After the e-beam exposure and subsequent development with a tetramethylammonium sulfate (TMAH) solution, the devices were inspected optically for residues and/or defects. The chips were then mounted on a 4” handle wafer and underwent an anisotropic ICP-RIE etch process using chlorine after qualification of the etch rate. The resist was removed from the surface of the devices using a 10:1 buffer oxide wet etch, and the devices were inspected using a scanning electron microscope (SEM) to verify patterning and etch quality. A 2.2 µm oxide cladding was deposited using a plasma-enhanced chemical vapour deposition (PECVD) process based on tetraethyl orthosilicate (TEOS) at 300ºC. Reflectometry measurements were performed throughout the process to verify the device layer, buffer oxide and cladding thicknesses before delivery. Washington Nanofabrication Facility (WNF) silicon photonics process: The devices were fabricated using 100 keV Electron Beam Lithography²⁰. The fabrication used silicon-on-insulator wafer with 220 nm thick silicon on 3 µm thick silicon dioxide. After a solvent rinse and hot-plate dehydration bake, hydrogen silsesquioxane resist (HSQ, Dow-Corning XP-1541-006) was spin-coated at 4000 rpm, then hotplate baked at 80°C for 4 minutes. Electron beam lithography was performed using a JEOL JBX-6300FS system operated at 100 keV energy, 8 nA beam current, and 500 µm exposure field size. The machine grid used for shape placement was 1 nm, while the beam stepping grid, the spacing between dwell points during the shape writing, was 6 nm. An exposure dose of 2800 µC/cm2 was used. The resist was developed by immersion in 25% tetramethylammonium hydroxide for 4 minutes, followed by a flowing deionized water rinse for 60 s, an isopropanol rinse for 10 s, and then blown dry with nitrogen. The silicon was removed from unexposed areas using inductively coupled plasma etching in an Oxford Plasmalab System 100, with a chlorine gas flow of 20 sccm, pressure of 12 mT, ICP power of 800 W, bias power of 40 W, and a platen temperature of 20°C, resulting in a bias voltage of 185 V. During etching, chips were mounted on a 100 mm silicon carrier wafer using perfluoropolyether vacuum oil. Cladding oxide was deposited using plasma enhanced chemical vapor deposition (PECVD) in an Oxford Plasmalab System 100 with a silane (SiH4) flow of 13.0 sccm, nitrous oxide (N2O) flow of 1000.0 sccm, high-purity nitrogen (N2) flow of 500.0 sccm, pressure at 1400mT, high-frequency RF power of 120W, and a platen temperature of 350C. During deposition, chips rest directly on a silicon carrier wafer and are buffered by silicon pieces on all sides to aid uniformity. Device measurement: Semi-automated grating coupled device measurements were performed at The University of British Columbia. A tunable laser (Agilent 81600B) and optical power meter (Agilent 81635A) were used to capture device spectra over the range 1500–1600 nm in 10 pm steps.

Acknowledgements

This work was supported by the Air Force Office of Scientific Research (AFOSR) Young Investigator Research Program (G. Pomrenke) and funds from Clemson University. The authors also acknowledge the edX UBCx Phot1x Silicon Photonics Design, Fabrication and Data Analysis course organized and operated by L. Chrostowski and I. Taghavi, which is supported by the Natural Sciences and Engineering Research Council of Canada (NSERC) Silicon Electronic-Photonic Integrated Circuits (SiEPIC) Program. The devices were fabricated by R. Bojko at the University of Washington Nanofabrication Facility (WNF) part of the National Science Foundation’s National Nanotechnology Infrastructure Network (NNIN), and C. Horvath at Applied Nanotools, Inc.

Competing Interests

The authors are pursuing a patent application, related to this work, with the U.S. Patent and Trademark Office

Author Contributions

YL and JR initiated and supervised the research and FB and JR designed the experiment. FB and AG developed and evaluated the analysis techniques with inputs from YL and JR. All authors collaboratively analyzed and interpreted the results. FB and JR prepared the manuscript with contributions/reviews from all authors.

Data Availability

The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.

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Competing interest reported. The authors are pursuing a patent application, related to this work, with the U.S. Patent and Trademark Office.

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Scalable and CMOS compatible hardware authentication using silicon photonic physical unclonable functions

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