2.1. Shared Charge Based Latched Dynamic Comparator [SCLDC]
Figure 1. demonstrates a dynamic comparator with a shared charged based scheme. This is dual tail dynamic comparator, it has two stages one is preamplifier and second is latch. In the latch stage a pass transistor (PMOS) is connected between two output terminals such that charges are shared between them in the reset phase. This helps to hold output above threshold voltage and thus, comparison is done faster in regenerative stage.
Figure 1's operation is as follows: At low clock (CLK = 0), the transistors Mc1 and Mc2 of regenerative latch stage and pre-amplifier stage respectively are OFF, thus not providing any path for current to flow and hence no static power dissipation is occurring in the circuit during reset phase [11]. The PMOS transistors M1 and M2 turn ON which pulls the terminals Yn and Yp to VDD. Yp and Yn terminals connected to M9 and M10 transistors respectively also turned ON both these transistors due to its charging up to supply voltage. PMOS transistor Mp is ON during low clock signal and it shorts the outp and outn such that charge is shared between the two output terminals. Both the output terminals are maintained near to half of the supply voltage. The main advantage of this charge shared circuit is no additional requirement of clock signal such as CLKB which avoids need of proper synchronization between signals thus optimizing power and delay [14].
When clock is high (CLK = VDD), the transistors Mc1 and Mc2 switch ON which provides path for current to flow. Transistor M1 and M2 are turn OFF which causes terminals Yn and Yp to discharge now [15].
The terminals Yn and Yp will not discharge at same rate instead their discharging will depend upon the input voltages (Vip and Vin). If Vip > Vin, Yn will discharge faster than Yp, in this way transistor M10 will turn OFF earlier than M9. Reverse would happen, if opposite case of input voltages is taken. One output will be pushed to reach VDD and the other output will be pushed to ground by the dynamic comparator's positive feedback mechanism during the regeneration step. This circuit causes output terminals to be at almost half of the supply voltages during the reset phase shown in Fig. 2 which is completely different from the conventional double tail dynamic comparator where decision is taken when output terminals are at extreme voltages [24]. This architecture helps in reducing delay and power.
2.2. Transconductance Enhanced Latched Dynamic Comparator (TELDC)
Based on separate gate biasing of the cross coupled transistors shown in Fig. 3, TELDC circuit improves the effective transconductance during comparison phase. The working of the circuit is: During the first phase of the circuit i.e., reset, when clock signal is low, NMOS transistor Mc1 is switch OFF and PMOS transistors M3 and M4 of the same stage turns ON which eventually pushes nodes Yn and Yp to charge to supply voltage[16]. Due to charging of nodes Yn and Yp to VDD, M11 and M12 are ON now which provides a discharging path to ground for nodes Cn and Cp. Due to its cross coupled topologies, transistors M5 and M6 switch ON via Cn and Cp and thus pulls up output terminals (outp and Outn) to charge up to VDD [17–18]. The introduction of the cross coupled structure in the regenerative latch stage provides higher transconductance than other conventional structures. This circuit leads to faster speed and also helps in reduction of the metastable state time period. The circuit has level shifted CLK2 signal which has been delayed by topt of CLK1 signal intentionally to make sure that transistor M7 and M8 are ON after short current flowing through transistor M11 and M12 are minimized during rising of CLK1 signal [19].
When clock signal is high (CLK1 = VDD), transistor Mc1 turns ON and M3, M4 switch OFF. Nodes Yn and Yp based on the rates of the input voltages, begins to decline [20],[21]. The output terminals outp and outn will now start to get discharged from VDD at different rates while nodes Cn and Cp starts increasing from ground. When CLK2 signal becomes active[25], turns M7 and M8 transistors ON which leads to fast discharging of output terminals to nodes Cn and Cp. During the start of the evaluation phase, this circuit provides high transconductance[22] than any other conventional structure. The transconductance enhanced dynamic comparator leads to high speed along with minimum energy consumption [23]. The simulation waveform is demonstrated in Fig. 4.
2.3. Proposed Dynamic Comparator
The proposed circuit is a combination of the shared charge logic(SCLDC) and transconductance enhanced latched dynamic comparator(TELDC). The regenerative latch stage of the transconductance enhanced dynamic comparator is backed up with shared charge technique in order to further optimize the delay of the circuit is demonstrated in Fig. 5.
The tail transistors Mc1 and Mc2 are turned off when the clock signal is low (CLK1 = 0), whereas M3, M4 are switched ON, pulling up the nodes Yn and Yp to VDD in similar way as explained in above cases. When M11 and M12 also turns ON in reset phase, then Cn and Cp discharge to ground and pass transistor Mp will short the terminals outp and outn such that these transistors will work as a shared charges between two terminals. Charge will be shared between two nodes as one of the outputs reach up to supply voltage and other drops to ground after the previous regeneration phase. The proposed architecture further enhances the effective transconductance of the circuit which eventually improves the speed.
During regeneration phase, when CLK1 is high, Mc1 and Mc2 are ON while transistors Mp, M3 and M4 are OFF. Yn and Yp will now start to get discharge from VDD, based on the input voltage. Cn and Cp starts to increase from ground. When CLK2 signal is active after some optimum delay then transistor M7 and M8 also switch ON, hence, outn and outp discharges to Cn and Cp very fast which causes very fast increment of drain to source voltages(Vds) of latch transistors. Due to this, the effective transconductance improves as it depends linearly on Vds. The simulation of the proposed comparator is demonstrated in Fig. 6. (a) and (b) for CMOS 45-nm and CNTFET 10-nm technology. The schematic remains same for the technologies.
The proposed comparator based on CMOS technology is simulated in Fig. 6(a) for VDD = 0.8V, Vcm = 0.7V, Vid = 5mV. The delay of this proposed design reduced with comparing to the TELDC simulation in Fig. 4. with same conditions. CNTFET based proposed design is simulated in Fig. 6(b) at the same condition with change in supply voltage (VDD). HereVDD is taken as 0.4V due to 10nm channel length of the CNTFET. Benefit of CNTFET based proposed design is that the power consumption has reduced significantly. Proposed design with CNTFET is working fine but it has problem of delay.
2.4. Mathematical Analysis of delay for Proposed Dynamic Comparator
The delay of the comparator is taken from the initiated clock signal to time when the difference between outputs reaches half of the supply voltage. Consider the supply voltage is VDD. For the proposed design delay (tdelay) is divided in to three parts, this is given in Eq. (1)
$${t_{delay}}={t_{opt}}+{t_{amp}}+{t_{latch}}$$
1
.
In Eq. (1) topt, is the time when the buffer is active due to which NMOS transistors M7 and M8 become ON. Buffer is used here to turn ON transistor M7 and M8 after the main clock CLK1. This delay is used here to reduce the short current through M9 and M10 at the rising CLK1 [25]. In this work a PMOS (Mp) is connected to the latch's output terminals. This is act as a charge share between two output terminals at the reset phase. Due to charge sharing, it is considerable that both the outputs of the latch maintain approximately VDD/2.
Second term in Eq. (1) is amplification stage delay (tamp), which is expressed in Eq. (2). The load capacitance CLOUT begins to discharge at the beginning of the evaluation phase from VDD/2 until the PMOS M5/M6 turn ON.
$${t_{amp}}=\frac{{\left( {\frac{{{V_{DD}}}}{2} - {V_{THP}}} \right) \times {C_{LOUT}}}}{{{I_1}}} \approx \frac{{2 \times \left( {\frac{{{V_{DD}}}}{2} - {V_{THP}}} \right) \times {C_{LOUT}}}}{{{I_{MC2}}}}$$
2
.
Where, VTHP is the threshold voltage of the (M5/M6). IMC2 is the tail current of the latch stage.
Where, IMC2 is illustrated in Eq. (3)
$${I_{MC2}}={I_1}+{I_2}$$
3
.
I 1 and I2 is the drain current of M9 and M10. If Vip > Vin, then I1 \(\approx\) IMC2/2, now put the value of I1 in Eq. (2) it is modified in Eq. (4)
$${t_{amp}}=\frac{{\left( {{V_{DD}} - 2{V_{THP}}} \right) \times {C_{LOUT}}}}{{{I_{MC2}}}}$$
4
.
I MC2 is written in terms of trans-conductance gmp in Eq. (5). In Eq. (6) effective trans-conductance gmeff term is used during the time of amplification stage gmeff = gmp + gmn, here the NMOS and PMOS of the latch stage is contributed in the gmeff. So, the value of the effective transconductance is increased. Due to increase in gmeff and charge share due to MP transistor there is reduction in tamp.
$${t_{amp}}=\frac{{({V_{DD}} - 2{V_{THP}}) \times {C_{LOUT}} \times 2{\mu _p}{C_{ox}}\frac{{{W_p}}}{{{L_p}}}}}{{g_{{mp}}^{2}}}$$
5
.
$$\approx \frac{{({V_{DD}} - 2{V_{THP}}) \times {C_{LOUT}} \times 2{\mu _p}{C_{ox}}\frac{{{W_p}}}{{{L_p}}}}}{{g_{{meff}}^{2}}}$$
6
.
The third term in Eq. (1) is latch delay (tlatch). This is the time required to reach the separation of the two output of the latch to VDD/2 from the initial value (△V0) of the latch. This is expressed in Eq. (7).
$${t_{latch}}=\frac{{{C_{LOUT}}}}{{{g_{meff}}}} \times \ln \frac{{{\raise0.7ex\hbox{${{V_{DD}}}$} \!\mathord{\left/ {\vphantom {{{V_{DD}}} 2}}\right.\kern-0pt}\!\lower0.7ex\hbox{$2$}}}}{{\Delta {V_0}}}$$
7
.
This delay changes in a logarithmic manner. △V0 is calculated in Eq. (8).
$$\Delta {V_0}=\left| {{V_{OUTP(t={t_{amp}})}} - {V_{OUTN(t={t_{amp}})}}} \right|$$
8
$$\Delta {V_0}=\left( {\frac{{{V_{DD}}}}{2} - {V_{THP}}} \right) - \frac{{{I_2} \times {t_{amp}}}}{{{C_{LOUT}}}}$$
9
$$\Delta {V_0}=\left( {\frac{{{V_{DD}}}}{2} - {V_{THP}}} \right)\left( {1 - \frac{{{I_2}}}{{{I_1}}}} \right)=\left( {\frac{{{V_{DD}}}}{2} - {V_{THP}}} \right)\frac{{\left( {{I_1} - {I_2}} \right)}}{{{I_1}}}$$
10
.
The difference in current △I = I1 – I2 and this is depend upon tans-conductance of gm11,12 and △VYp,Yn which is the voltage difference between the internal nodes (Yp and Yn) of the proposed comparator.
Hence, I1 – I2 = gm11,12×△VYp,Yn
Yp and Yn are the internal node of the proposed comparator. Now place the value of I1 – I2 in Eq. (10).
$$\Delta {V_0}=\left( {{V_{DD}} - 2{V_{THP}}} \right) \times \frac{{{g_{m11,12}}}}{{{I_{MC2}}}} \times \Delta {V_{Yp,Yn}}$$
11
.
The value of △VYp,Yn is generated due to the difference in the current due to differential voltage △Vi. △VYp,Yn is expressed in Eq. (12). Where CLYp,Yn is the load capacitance of the internal nodes (Yp and Yn).
$$\Delta {V_{Yp,Yn}}=\frac{{{g_{m1,2}} \times \Delta {V_i} \times {t_{amp}}}}{{{C_{LYp,Yn}}}}$$
12
.
$$\Delta {V_{Yp,Yn}}=\frac{{{g_{m1,2}} \times \Delta {V_i}}}{{{C_{LYp,Yn}}}} \times \frac{{({V_{DD}} - 2{V_{THP}}) \times {C_{LOUT}} \times 2{\mu _p}{C_{ox}}\frac{{{W_p}}}{{{L_p}}}}}{{g_{{meff}}^{2}}}$$
13
.
$$\Delta {V_0}=\left( {{V_{DD}} - 2{V_{THP}}} \right)\frac{{{g_{m1,2}} \times \Delta {V_i}}}{{{C_{LYp,Yn}}}} \times \frac{{({V_{DD}} - 2{V_{THP}}) \times {C_{LOUT}} \times 2{\mu _p}{C_{ox}}\frac{{{W_p}}}{{{L_p}}}}}{{g_{{meff}}^{2}}}$$
14
$$\Delta {V_0}={\left( {{V_{DD}} - 2{V_{THP}}} \right)^2} \times \frac{{{g_{m11,12}}}}{{{I_{MC2}}^{2}}} \times \frac{{{g_{m1,2}}\Delta {V_i}}}{{{C_{LYp,Yn}}}} \times {C_{LOUT}}$$
15
.
The final value of △V0 is expressed in Eq. 15. This value is increased due to charge share transistor, △V0 is directly proportional to the square of the VDD – 2VTHP and the product of two trans-conductance of gm11,12 and gm1,2. Due to this the latch reaches to VDD/2 faster and delay time of comparator reduces.
Now put the value of tamp and tlatch into Eq. (1), then Eq. (1) becomes modified as Eq. (16) and Eq. (17).
$${t_{delay}}={t_{opt}}+\frac{{\left( {{V_{DD}} - 2{V_{THP}}} \right){C_{LOUT}} \times 2{\mu _p}{C_{ox}}\frac{{{W_p}}}{{{L_p}}}}}{{g_{{meff}}^{2}}}+\frac{{{C_{LOUT}}}}{{{g_{meff}}}} \times \ln \frac{{{\raise0.7ex\hbox{${{V_{DD}}}$} \!\mathord{\left/ {\vphantom {{{V_{DD}}} 2}}\right.\kern-0pt}\!\lower0.7ex\hbox{$2$}}}}{{\Delta {V_0}}}$$
16
.
$$\begin{gathered} {t_{delay}}={t_{opt}}+\frac{{\left( {{V_{DD}} - 2{V_{THP}}} \right){C_{LOUT}}}}{{{I_{MC2}}}}+ \hfill \\ \frac{{{C_{LOUT}}}}{{{g_{meff}}}}\ln \frac{{{V_{DD}}I_{{MC2}}^{2}{C_{LYp,Yn}}}}{{2{{\left( {{V_{DD}} - 2{V_{THP}}} \right)}^2}{g_{m11,12}}{g_{m1,2}}\Delta {V_i}{C_{LOUT}}}} \hfill \\ \end{gathered}$$
17