According to the Wentzel–Kramers–Brillouin (WKB) approximation an expression for transmission probability (Tt) for TFET is derived assuming the tunnel barrier as a triangular-shaped potential barrier [24].
IBTB\(\propto\) Tt \(\approx exp\left(-\frac{4\lambda \sqrt{2{m}^{*}} {E}_{g}^{3/2} }{3ħ \left(\varDelta \varPhi +{E}_{g}\right)}\right)\) …… (1)
Where \(\lambda\) is the Debye length m* is the effective mass, \({E}_{g}\) is the energy bandgap between the valance band and conduction band, \(ħ\) is plank constant and \(\varDelta \varPhi\) is the energy range.
The purpose is to take advantage of increasing the electric field at the tunneling junction, which will improve transmission probability and hence increase the band to band tunneling current. This has been accomplished before, by using dual k-spacers between gate and source [36]. In this work, the use of dual material double gate with a P + pocket embedded in the source side efficiently enhanced the electric field, assisting with tunneling as shown in Fig. 2a. Due to the presence of a pocket and dual material gate, the hole concentration at the source edge and the electron concentration at the gate edge adjacent to the tunneling junction increase when the gate voltage is applied (Fig. 2b). Dashed lines are indicated as hole concentration while the solid lines depict the electron concentration. Figure 2c illustrates the formation of sufficient electron and hole concentrations of all TFET devices, as well as the development of the n-i-p + structure required for tunneling. To enhance the performance of the conventional device we have taken the optimized value of P + pocket length (LP) of 5 nm on the source side with doping concentration 1021cm-3 and P-gate work function of\({ \varnothing }_{PG}=3.9 eV\). All the graphs were taken at cutline 1 nm below semiconductor-insulator contact (Si-SiO2). In Fig. 2c, the energy band diagram with device length of SMG, PP-SMG, DMG, and PP-DMG are plotted. The slope of the energy bands in the ON state reflects the increase in electric field and carrier concentration in the vicinity of the tunnel barrier.
TABLE-1 Device structure parameters
PARAMETERS
|
VALUE
|
Drain length (LD)
|
40 nm
|
Gate length (LG)
|
40 nm
|
Source length (LS)
|
40 nm
|
Drain to gate gap length (LGAP,D)
|
15 nm
|
Gate to source gap length (LGAP,S)
|
5 nm
|
Oxide thickness (TOX)
|
1 nm
|
Silicon thickness (TSi)
|
10 nm
|
Intrinsic carrier concentration (ni)
|
1015 cm− 3
|
Drain electrode work function (ØD)
|
3.9 eV
|
Gate electrode work function (ØG)
|
4.5 eV
|
Source electrode work function (ØS)
|
5.93 V
|
When comparing PP-DMG to other devices in ON-state, there is a considerable reduction in tunnel barrier. Due to the low \({\varnothing }_{PG}\) and p-pocket, a higher number of electrons tunnel from the source valence band to the channel conduction band. Therefore, the ON-state current is amplified as compared to SMG, PP-SMG, and DMG. The electric field is significantly increased due to the lower work function of the p gate in DMG architecture with a P + pocket in the DMG TFET.
In Fig. 3a and b, we can see that the drain current of PP- DMG on a linear and log scale respectively is significantly high in the ON-state device which is attributed to the P + pocket in the source side and dual material at gate voltage (VGS=1V, VDD=1V). The ON current is dependent on the width of the tunneling barrier, as discussed earlier this tunneling barrier width is reduced due to the low work function of the P gate with a P + pocket. We measured performance matrices such as ION IOFF etc, at different P gate work-function but the optimized result was obtained for PP-DMG at ɸPG=3.9eV. The ON current improved approximately by 2 orders for PP-DMG as compared to SMG and considerably large with respect to all the devices mentioned in this paper. The subthreshold swing for PP-DMG also improved such as the point subthreshold swing (SSpt) is 15.3mV/dec and the average subthreshold swing (SSAvg) is 18.6mV/dec which is less than 60mV/dec among all devices shown in table-II. Due to the increment of drain current in PP-DMG, the gate capacitance has also increased. To incorporate the effect of Cgg, we have calculated the factor Ion/Cgg. A higher value of Ion/Cgg shows better drive strength of the device. The value of parameter Ion/Cgg, is highest for PP-DMG in comparison to other devices as illustrated in Fig. 3d. The transconductance Gm., which is defined as Gm= dId / dVgs for a particular drain to source voltage Vds and cut off frequency (fT= Gm/2Cgg), is one of the major enhancements to assess the RF/
TABLE-II Subthreshold Slope
DEVICE
|
SSpt
|
SSAvg
|
PP-DMG
|
15.3 mV/dec
|
18.6 mV/dec
|
DMG
|
22.6 mV/dec
|
25 mV/dec
|
PP-SMG
|
20.8 mV/dec
|
37.7 mV/dec
|
SMG
|
21.6 mV/dec
|
40.5 mV/dec
|
Analog performance. (The gate capacitance is Cgg.). Figure 4 (a) shows the Gm of the devices. For PP-DMG, Gm has increased drastically as compared to all other devices because the low workfunction p-gate and P + Pocket provide higher drive current at all gate voltages. This parameter is quite advantageous in the RF/analog domain because the gain of an analog circuit is primarily determined by transconductance Gm which is the most important parameter for the design of an analog circuit. Figure 4b shows the cutoff frequency (fT). The proposed PP-DMG shows very high fT as compared to other devices due to higher injection of charge carriers from the source and it becomes saturated at high Vgs because of the combined effect of Gm. Figure 4c shows the device efficiency (Gm/Id). The proposed PP-DMG device shows very high device efficiency as compared to other devices for different work functions. High device efficiency (Gm/Id) is due to the lower tunneling gate work function.
Aside from device efficiency, the transconductance frequency product (TFP) is also an important measure for device RF analysis. In Fig. 4d, it can be seen that the PP-DMG shows higher TFP characteristics in comparison to other devices due to higher device efficiency and transconductance. These analyzed parameters give robust results for the analog/RF domain which can help in the future.
Finally, we studied the nonlinearity and distortion analysis of all the devices. We analyzed the linearity and distortion parameters of all devices in terms of gm3, VIP2, VIP3, third-order input intercept point (IIP3), and intermodulation distortion (IMD3), which are clearly explained and formulated in [24] and [25]. The gm3 coefficient of conventional (SMG and DMG) and proposed devices (PP-SMG and PP-DMG) as a function of gate bias is shown in Fig. 5. It can be deduced that the proposed PP-DMG device’s gm3 peak and zero crossover point are attained at a lower gate bias than its counterpart devices.
The VIP2 properties of all devices as a function of gate bias are shown in Fig. 6a. For high linearity and low distortion, VIP2 and VIP3 should be as high as possible. The proposed device, PP-DMG VIP2 amplitude is much greater than all other devices. In a similar vein, the proposed device PP-DMG VIP3 is higher than the other devices, as seen in Fig. 6b. Furthermore, the installation of a dual material gate with a p + pocket in the proposed device raises the maximum value of VIP3. Therefore, the suggested device's higher VIP3 peak implies that the device cancels the third-order transconductance coefficient [24]. Furthermore, the proposed device PP-DMG VIP3 peak shifts toward lower gate voltages and its higher amplitude is reached at lower gate bias, implying that excellent linearity may be attained at lower gate bias when compared to other devices.
We have computed IIP3 and IMD3, IIP3 comes into play in RF devices as a result of ac nonlinearity at the input frequency and the frequency difference between two neighboring signals [24]. Also, the signal in the next channel in wireless transceivers can be corrupted by third-order intermodulation distortions caused by the nonlinearity of the device Id–Vgs characteristics [25]. Thus, IMD3, which is produced as a result of nonlinearity in the device's static properties, is also investigated. So, we investigated these two critical parameters (IIP3 and IMD3) in depth. For better performance of the device in circuit applications, IIP3 should be high whereas IMD3 should be minimum for the lower distortions. Figure 6c and 6d show the graphs of IIP3 and IMD3 as a function of gate bias for both devices. It can be seen that PP-DMG has the highest IIP3 values than the other devices. However, for PP-DMG IIP3 peak shifts toward lower gate bias, indicating that excellent linearity may be attained with lower gate voltages. This is owing to the inclusion of a dual material gate with a p + pocket, which reduced the hot-carrier effect and increased device power, resulting in higher linearity. Furthermore, the PP-SMG device has the lowest distortion (IMD3) whereas PP-DMG has the highest. Finally to show the effect of process variation (here in this case variation of LP) on drain current and cutoff frequency we have investigated the variation of p+ pocket length. The drain current and cut-off frequency are almost the same with a variation of pocket length (1-5nm variation). This indicates that the drain current and cut-off frequency are immune to variations in pocket length.