112G baud sub pJ/bit integrated CMOS-silicon photonics transmitter

doi:10.21203/rs.3.rs-1980286/v1

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112G baud sub pJ/bit integrated CMOS-silicon photonics transmitter

https://doi.org/10.21203/rs.3.rs-1980286/v1

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published 23 Oct, 2023

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A new design philosophy for integrated CMOS-silicon photonic transmitters is introduced where switching current is applied to the silicon Mach Zehnder Modulator (MZM) rather than operating in the traditional voltage driving mode. With this approach the total electrical energy can be selectively distributed to different frequency components by choosing appropriate inductance and near-end termination impedance values. 112G baud (112Gb/s OOK and 224Gb/s PAM-4) transmission has been experimentally demonstrated with a real power efficiency down to the sub pJ/bit regime without the requirement for power hungry pre-emphasis or signal shaping in the data source. A thorough investigation of the BER for different electrical and optical power conditions of our fully integrated optical transmitter at 100G baud + is performed including the electrical power consumption of the driver which is often neglected in other work.

The relentless growth in data demand has pushed transmission rates of optical technology within ICT infrastructure to 100G baud and beyond. Producing devices to support such speeds is however not trivial with such high frequency operation often coming at the expense of power consumption for any signal shaping and equalisation or to mitigate problems arising from device parasitics. Whilst increases in data capacity are essential to meet future demands, power consumption has become a major global concern. Projections are that ICT infrastructure could use up to 21% of global electricity by 2030¹. It is therefore essential to understand practical limitations of photonics technology in terms of both, speed and power consumption, paving a path to power efficient 100G baud operation.

Recently substantial research effort has been devoted to high baud-rate optical transmitters. Typical solutions include Directly Modulated Lasers (DMLs)^{2 3}, thin-film lithium niobate ^4–7 plasmonics ^{8 9}, polymers ¹⁰, Indium Phosphide (InP) ^{11 12}, Electro-Absorption Modulators (EAMs) ¹³, silicon-based Ring Resonator Modulators (RRMs) ^14–16 and silicon-based Mach–Zehnder modulators (MZMs) ^{17 18}. Whilst most demonstrations have highlighted an outstanding bandwidth or throughput performance, a fundamental understanding of the electrical power required for 100G baud + transmission is lacking. Previous optical transmitter device reports have tended to estimate consumption figures only based upon the device capacitance and/or required drive voltage, often indicating power levels down to fJ`s/bit. However, the power consumed within other functions needed for device operation at the required performance has not been considered. As has been indicated in ¹⁹, the power efficiency of the photonic device alone corresponds to the energy associated with changing the charge density and does not include the power consumption of a real broadband amplifier. Even if these small figures (fJ/bit) are considered the theoretical power efficiency limit of the photonic device, the awkward fact is that a broadband amplifier's output power efficiency (the ratio of output power to overall power consumption) could be < 4%²⁰ for millimetre wave operation. Therefore, such devices need driver amplifiers with Watt level power consumption for 100G baud + data transmission. This together with the energy consumed within any required Arbitrary Wave Generators (AWG) or Digital-to-Analog Converters (DAC) would likely result in a real power efficiency exceeding tens of pJ/bit. The true power consumption figure of an optical transmitter should therefore include the power consumed by the driver amplifier, operating point tuning (e.g. heating element) and any preceding signal processing functions, such as signal shaping or equalisation functions within DAC or AWG.

Real sub-pJ/bit power efficiency has been reported within packaged silicon photonics transmitters^{21 22}, however they have been limited to lower baud rates (approx. 20G baud) since device and parasitic capacitances act as a dominant low impedance load at higher frequencies leading to sharp increases in power consumption. Furthermore, parasitic effects associated with electronic-photonic integration pose further challenges for low power operation at 100GBaud+.

In this work, a comprehensive design philosophy for all-silicon optical transmitters is introduced. Based on this platform (28nm bulk CMOS + silicon photonics), the proposed solution has achieved 112G baud (112Gb/s OOK and 224Gb/s PAM-4) transmission. The true power consumption limits are investigated at 100G Baud and beyond with a real power efficiency that is sub-pJ/bit without the need for pre-emphasis or signal shaping in the data source. Minimising the power consumption of the driver amplifier could directly degrade the Signal-to-Noise-Ratio (SNR) and therefore the Bit-Error-Rate (BER). The trade-off between electrical power efficiency and average received optical power for a full transceiver link is therefore also experimentally investigated.

Design considerations for optical modulators, especially silicon MZMs, have been thoroughly analyzed for decades^19,23. Solutions and circuit topologies for electrical broadband amplifiers are even more mature, dating back to the 1940s²⁴. However, to date similarities between these two modules have not been explicitly evaluated.

The pre-condition for electrical amplifiers to operate properly is appropriate DC biasing of its internal transistors. As indicated in Fig. 1(a), the DC voltage difference between gate (V_G) and source nodes (V_S) should be larger than the threshold voltage (Vth) of the transistor (expressed as V_GS≥Vth). Similarly, as shown in Fig. 1(b), for depletion mode PN junction based silicon optical modulators, the pre-condition is that they should be reverse biased, i.e. the N node is at a higher voltage than the P node. Tuning the DC bias considerably changes the intrinsic bandwidth of both the transistor and modulator. For the 28nm CMOS process, the NMOS transistor transition frequency (f_t) could reach 270GHz, with the Gate (V_G) and Drain (V_D) biased at 0.7-0.8V. Similarly, the intrinsic bandwidth of the modulator cross-section (in depletion mode) developed in this work was found to be 70GHz to 160GHz with a reverse bias between 1V and 8V (See Methods section-II).

For an NMOS based broadband common-source amplifier, as long as the transistors are properly DC biased, they have a fixed gain-bandwidth product with a larger width providing larger voltage gain but smaller bandwidth. When the electrical amplifier sees a low impedance load and delivers usable voltage gain, the typical 3dB bandwidth of the amplifier is within the range of tens GHz, although the intrinsic frequency of the NMOS transistor itself could reach several hundred GHz. A similar phenomenon occurs with the silicon MZM. With a given input voltage swing (Vin), the extinction ratio is proportional to the phase shifter length, but the EO bandwidth is inversely proportional. When the silicon MZM delivers a useable modulation depth with a practical input voltage swing, the achievable EO bandwidth is within the range of tens GHz, although the intrinsic bandwidth of the modulator can be much higher than 100GHz. If the requirement for the voltage swing and modulation depth are omitted allowing the phase shifter length to be short (100µm range) then EO bandwidths > 100GHz are possible²⁵.

Furthermore, for a properly DC biased electrical amplifier, increasing the transistor's width normally results in higher power consumption and larger layout area. Similarly, increasing the phase shifter length will lead to higher optical loss and a larger footprint. In summary, both the electrical amplifier and silicon MZM exhibit similar performance trade-offs. Performance enhancement techniques and design philosophies that have matured for electrical amplifiers could therefore be utilized to develop silicon MZM. Following this concept, an initial attempt ²⁶ was to adopt an inductive network (T-coil peaking) ²⁷ within the silicon MZM and driver amplifier interface as shown in the right of Fig. 1(b). This enabled demonstration that all-silicon optical transmitters can operate at 100G baud OOK with sufficient ER.

For power efficiency improvements within optical transmitters, the intuitive solution is to again reference successful design approaches developed for electrical amplifiers. An example widely adopted in analogue amplifier design is the "gm/I_D" approach^28,29. The core concept is not to pursue minimum current flow but to find the optimal point to maximise the utilization of current flow through the transistor. The transistor size is therefore selected based upon the ratio of transconductance (gm) to DC current (I_D).

In contrast, optical modulator designers usually target an absolute figure, such as "small Vpi" or "large EO bandwidth", rather than considering how the electrical energy is dissipated within the modulation procedure itself. The generation of a high voltage swing (V_in+/V_in-) signal at 100G + Baud already requires a power-hungry driver. As depicted in Fig. 1(c), this signal then suffers significant attenuation when propagating along the modulator electrodes with higher attenuation at higher frequencies resulting in a bandwidth-limitation. From a power efficiency perspective, most of the energy associated with these high-frequency components is actually dissipated within the electrodes rather than contributing to optical phase change. To compensate the bandwidth drop, a common approach is to adopt pre-emphasis or equalization techniques before the driver, but these also come at the expense of power efficiency.

A better approach is to consider the phase shifter, inductive network, far-end termination (R₂) and near-end termination (R₁) as an "integrated optoelectronic device" and apply a pair of switching currents (I_in+/I_in-). The electrical energy can then be distributed to different frequency components by changing the near-end termination impedance (R₁) and dimensions of the inductive network. This phenomenon is conceptually illustrated in Fig. 1(e), where the inductive peaking network dimensions are fixed, while the near-end termination impedance (R₁) is varied from $\infty$ to $0$. When the near-end termination (R₁) is $\infty$, the effective circuit diagram is similar to the cases where an open-drain amplifier (open collector amplifier for a BiCMOS process) is integrated to an MZM ^30–33. This is normally considered a power-efficient design since the driver amplifier only sees one termination load (R₂), however, as highlighted by the dark blue curve of Fig. 1(e), most energy is distributed to low-frequencies. Author ³¹ for example, therefore needed to incorporate an additional high-frequency peaking function within the pre-driver stages, which then consumed additional power.

Some common design guidelines are still valid, including effective index matching among optics and electronics, impedance matching between the far-end termination (R₂) and characteristic impedance (Z₀) of coplanar waveguide electrodes (CPW). The major change in the design philosophy is that we are neither concerned about the peak-to-peak voltage swing (Vpp) generated from the driver amplifier or the impedance matching between the near-end termination (R₁) and CPW characteristic impedance (Z₀). Instead, within the amplifier design, the design targets are the values and signal integrities of the switching currents (I_in+/I_in-) that are applied to the "integrated optoelectronic device". Within the modulator, besides optical phase shifter optimization itself, the value of the near-end impedance (R₁) and inductive peaking network dimensions are then co-designed based on the RF loss profile of the modulator, so that the majority of the energy (switching current) is delivered across the modulator causing optical phase change over the desired frequency band.

To justify the proposed design philosophy and investigate the power efficiency limits of all-silicon optical transmitters at 100G Baud+, a set of silicon photonics MZMs have been fabricated (See Methods section-I) within the same wafer that not only covers a range of phase shifter lengths(1.00mm, 1.27mm, 2.00mm, 2.47mm) for OOK, but also combine two different phase shifter lengths (1.27mm + 2.47mm) as a segmented modulator for PAM-4 (Fig. 2(g)). Regular standalone MZMs with phase shifter lengths of 1.00mm and 2.00mm were also fabricated to extract the fundamental performance parameters (optical insertion loss and Vpi·L) and compared with the devices (Fig. 2(e.f)) that are co-packaged with driver amplifiers.

The passive electrical components highlighted in Fig. 1(d), including the inductive network and terminations (R₁/R₂), were realized within the electrical CMOS process (TSMC 28nm HPC+, 1P8M5X1Z1U). To accommodate the E-O integration process (See Methods section IV) and to enable independent DC signal routing for each CMOS chip, the optical path (waveguide and phase-shifter) of the segmented modulator has been carefully designed, which is highlighted in Fig. 2(d). To enhance signal integrity and minimize the slot-line mode within the CPW^34,35, gold-wire based air-bridge bonding was deployed on all samples. These air-bridges could also be implemented within photonic chip fabrication process if multiple metal layers are available within the backend. The whole electronic chip is designed via a standard analogue/RF IC design flow, which is detailed in Methods section III.

The performance of the co-packaged all-silicon transmitters (1.27mm U-shape and 2.47mm U-shape) are analyzed and compared with regular standalone MZMs (1mm and 2mm). Firstly, the device EO response is tested with different reverse bias voltages (Fig. 3(a-d)). As expected, the 3dB EO bandwidths of the two co-packaged silicon transmitters are considerably higher than the standalone devices. Comparing the EO response at 65GHz, the two co-packaged devices are at -3dB and − 4.1dB (1.27mm and 2.47mm respectively), whereas the two standalone devices are at -3.6dB and − 8.2dB (1mm and 2mm respectively). The co-packaged 2.47mm version is just 0.5dB lower than the 1mm standalone device shown how the trade-off between phase shifter length and the EO bandwidth has been significantly alleviated within the frequency range up to 65GHz with our approach.

The primary research target was to improve the power efficiency and therefore we have characterized the properties of the eye-diagrams of all devices from 5Gbaud to 112Gbaud (the maximum speed of the testing equipment) while sweeping the power supply level to the CMOS chip. The recorded Extinction Ratio (ER) results are summarized in Fig. 3 (f/g), with ten selected eye diagrams highlighted in Fig(h). To ensure fair comparison, the operating point of all devices was tuned to the quadrature point(pi/2), which leads to 5-30mW power consumption in the heating element. Since the phase error in each device is different the required heating power in each case will also be different. To fairly compare the power consumption of each device variant the heater power is therefore neglected in the "power consumption" results shown in Fig. 3/4/5. These results include the overall power consumption of the CMOS driver chip only, where the current flow through the main power supply (1.5V-2.5V) is recorded as the "switching current". Within Fig. 3 (f/g), when operating at 112G baud (OOK mode), the power efficiency of both devices is calculated and highlighted under different switching current conditions. The best power efficiency is as good as 0.7pJ/bit with the resulting eye-diagram clear and open. The modulation depth of both devices is proportional to the switching current and longer devices provide larger modulation depths for a similar amount of switching current.

For comparison we tested the standalone MZMs (1mm and 2mm) using a commercial 100G-baud driver (SHF 840A) with the output swing fixed at 2.8Vppd. The two thick red curves in Fig (f/g) show their ER performance with baud rate, and the eye-diagrams at their highest baud rates are compared with two co-packaged devices at a similar ER in Fig. 3(h). When conducting these tests, the commercial driver consumes approximately 3.6W of power, which is at least 20 times higher than the driver developed in this work. It is obviously unfair to compare the absolute power efficiency between the commercial driver and the EO co-packaged circuit developed in this work, as the commercial driver is capable to provide a higher voltage swing and incorporates additional digital control modules. But the sharp ER roll off with speed already indicates that the voltage driving mode is not the optimal way to implement an all-silicon optical transmitter.

One concern with our approach is that ringing or overshooting may exist within the waveform as an impedance mismatch exists. Therefore, in the middle of Fig. 3(h), two 5Gb/s eye diagrams with the maximum and minimum switching currents are shown. An almost perfect square wave eye diagram demonstrates the accuracy of our analytical model and alleviates concerns regarding any near-end interface impedance mismatch.

Trade-off between electrical power and optical power

The peak optical insertion loss of the co-packaged 1.27mm and 2.47mm MZMs is 3.7dB and 6.9dB, respectively, including losses from MMIs, passive waveguides and phase shifters. An additional 12-13dB of optical loss comes from the two grating couplers. Therefore, when conducting eye-diagram testing, an EDFA is used to ensure the received optical power is maintained at 8dBm. This obviously leads to concerns about the link budget and real BER performance at the receiver side, which is directly related to the average optical power and the electrical power consumed on the transmitter side. Previous work^36,37 investigated this important relationship simply based on the estimated voltage swing applied to the modulator. However, they did not calculate the real power consumption of the driver amplifier and the results obtained also heavily relied on DSP, a power-hungry function that is also not factored into the power calculation. In this work, we have comprehensively evaluated this relationship by sweeping the EDFA gain and the power supply of the driver to show the trade-off between the received optical power(0dBm—8dBm) and power efficiency(0.7pJ/bit—1.54pJ/bit) of the electrical amplifier.

The results are summarised as a BER contour plot at the receiver when operating at 112G baud (Fig. 4 (a/b)), with ten selected eye diagrams and optical modulation amplitude (OMA) results highlighted in Fig. 4 (c-l). The photodetector (XPDV3120) used comes with a built-in 50ohm output load and when connected to the 50ohm electrical port of the DCA, the photodetector sees an effective load of 25ohm, which significantly degrades the SNR. The SNR can be significantly enhanced by incorporating an integrated high-speed detector and TIA³⁷. Even with such an imperfect testing environment, both devices achieve a BER level down to 2e^-7 with an electrical power efficiency of 1.54pJ/bit. When the driver power is reduced to 0.7pJ/bit, the recorded BER are 2e^-3 and 9e^-4 for the co-packaged 1.27mm and 2.47mm long MZMs, respectively, which are both better than HD-FEC limits (3.8e^-3). Even if an additional worst case 30mW power (2pi tuning) from the heater is included the power efficiency of both devices is still lower than the pJ/bit level.

More meaningful information comes from comparing the two devices when operating under the same electrical and optical power conditions. In Fig. 4(c/e, d/f, i/k, j/l), the 2.47mm MZMs can achieve almost twice the OMA of the 1.27mm MZM across all power conditions and hence provides a superior BER performance in all scenarios. This is understandable as longer devices provide a better modulation depth, and the designed inductive peaking network significantly alleviates the bandwidth drop experienced as the length is increased. However, among the different power conditions on a particular device, the operating point of the electrical amplifier has a more dominant effect on the BER performance. This phenomenon is highlighted in Fig. 4 (e/g/h), all of which come with the same BER level (1e^-3). The minimum electrical power condition requires 33mV OMA (Fig. 4(h)), whereas the other two cases only need 15mV (Fig. 4(e/g)). This is mainly because the transistor M1 within the electrical driver suffers a drop in transconductance(gm) when the current flow is reduced towards the lower end (minimum power case).

For PAM-4 testing, a second 100G MUX supplied the data source for the second modulator segment, and a passive RF phase tuner was used to adjust its timing delay. To compensate non-linearity within the MZM, a slightly lower voltage swing was applied to the short segment. Following the similar testing procedure as with the OOK devices, the segmented PAM-4 device (Fig. 2(g)) was characterized over different power conditions at 200Gb/s PAM-4 and 224Gb/s PAM-4. Their BER contour plots are shown in Fig. 5 (a/b), with selected eye diagrams shown in Fig. 5(c-j). When operating at the highest power conditions, the recorded BER is 1.8e^-3 (1.68pJ/bit) for 200Gb/s PAM-4 and 8.5e^-3 (1.51pJ/bit) for 224Gb/s PAM-4, which are both far better than the SD FEC limits(2e^-2). When operating with lower power consumption(< 0.9pJ/bit), the recorded BER is 3.5e^-2 for 200Gb/s PAM-4 and 4.5e^-2 for 224Gb/s PAM-4, which are both better than the 25% FEC limits(5e^-2). Even if 30mW of heater power is included, the overall power efficiency is still better than 1 pJ/bit. A key point is that all results shown here have been obtained without signal shaping or DSP in the transmitter side, only FFE has been adopted but without any other DSP within the receiver. Furthermore, if the near-end termination and inductive network had dedicated designs for the different phase shifter lengths, we anticipate the EO bandwidth of the longer segment(2.47mm) could be further optimized, and the overall BER performance would be improved.

Lastly, Table 1 compares the performance of this work to state-of-art results published in recent years using different types of optical transmitters. For fair comparison, the heater power is neglected in each case. It should also be highlighted that this is the first EO integrated optical transmitter that operates at 112G baud with a real power efficiency in the sub-pJ/bit regime, and for a comparable BER level previous demonstrations have almost an order of magnitude high power consumption and also require additional DSP on top of this.

Table 1

Comparison of key performance parameters for 100G + optical transmitters
Platform and type	Data rate (bits/s format)	DSP at Tx	DSP at RX	Driver Type/ Model No.	Driver Power	EO integration	Power Eff.
LiNbO3 (MZI) ⁵	100G OOK 112G PAM4	NA	Off-line DSP LMS equalizer 31 taps	SHF-807	3.60W	NO	> 32pJ/bit
Polymer (MZI) ¹⁰	200G PAM 4	Off-line DSP raised cosine filter	Off-line DSP linear equalization	SHF-804B	2.00W	NO	> 10pJ/bit
DML ²	256G PAM-4	NO	Off-line DSP 101 tap linear,61 tap non-linear equalization	SHF-840M	1.25W	NO	> 4.80pJ/bit
SOI (RRM) ¹⁶	120G OOK 220G PAM-4 240G PAM-8	Off-line DSP pre-equalization	Off-line DSP NN + MLSE	SHF-807C	3.00W	NO	> 12.50pJ/bit
GeSi EAM ¹³	224G PAM-4	Off-line DPS pulse shaping/Pre-emphasis	Off-line DSP FFE DFE PNLE	SHF-804B	2.00W	NO	> 8.92pJ/bit
SOI (MZI) ³⁸	64G OOK 138G PAM-4 102G PAM-8 408G DP-64QAM	DSP equalization	Coherent DSP	130nm SiGe BiCMOS	0.66W¹	Yes (Flip-chip)	7.35pJ/bit
SOI (RRM) ³⁹	112G PAM-4	NO	5 tap TDECQ filter	28nm CMOS	0.16W¹	Yes (Flip-chip)	1.43pJ/bit¹
MOSCAP (MZI) ⁴⁰	100G PAM-4	NO	5 tap TDECQ filter	28nm CMOS	0.108W¹	Yes (Flip-chip)	1.08pJ/bit¹
Plasmonic (MZI) ⁹	120G OOK	NO	Off-line DSP 101 tap	Bipolar	0.900W¹	Yes (Monolithic)	7.50pJ/bit¹
SOI (MZI) ²⁶	112G OOK	NO	7 tap FFE	28nm CMOS	0.178W²	Yes (Flip-chip)	1.59pJ/bit²
This work SOI(MZI)	112G OOK	NO	6 tap FFE	28nm CMOS	0.045W¹ 0.078W²	Yes (Flip-chip)	0.40pJ/bit¹ 0.70pJ/bit²
This work SOI(MZI)	200G PAM4	NO	12 tap FFE	28nm CMOS	0.107W¹ 0.177W²	Yes (Flip-chip)	0.54pJ/bit¹ 0.88pJ/bit²
This work SOI(MZI)	224G PAM4	NO	12 tap FFE	28nm CMOS	0.122W¹ 0.190W²	Yes (Flip-chip)	0.54pJ/bit¹ 0.855pJ/bit²
¹ Output stage only ² Power consumption includes DC biasing, pre-driver and output stage

A new design philosophy of silicon modulators is introduced. For this proof of concept, the inductive networks and termination resistors have been realized within the CMOS driver chip. Using this approach transmission up to 112Gb/s OOK and 224Gb/s PAM4 has been demonstrated from our all silicon integrated transmitter with power consumption down to the sub pj/bit range. The trade-off between power consumption and BER for different optical power levels has been comprehensively studied, also comparing devices of different length. As expected a larger power consumption leads to a superior BER performance, however due to bandwidth compensation in the driver longer lengths can give a better BER performance for a given power consumption. A key strength of our approach is that all results have been obtained without the requirement of signal shaping or DSP in the transmitter side, only FFE has been adopted but without any other DSP within the receiver. In future iterations it would be more economical and reasonable to implement the inductive networks and termination resistors within photonics chip, as they are compatible with standard back-end processes and occupy a footprint in micrometer range. When targeting different applications in different frequency bands the optical modulator design involves not only optimization of the phase shifter but also careful selection of the termination resistor values and optimization of the inductive network. The electrical driver provides the required switching current and should be designed with knowledge of the E/O integration process and related parasitic.

Observing the development of silicon photonics over the past few decades, besides evolutions in the absolute bandwidth, modulation format and power efficiency, the process and design of EO integration have gathered increasingly more attention. Integration was originally referred to as the physical coupling approach between photonics and electronics devices, such as wire-bonding, flip-chip bonding and monolithic integration where electrical connections are made within the metal layers of the chip. The concept of co-design of the photonic and electronics was then an important step to boost performance for a variety of applications. Now, perhaps it is time to bring design concepts from electronics IC design into photonic component and circuit design to enable the next leap in performance.

I Photonics device fabrication. The photonic integrated circuit (PIC) was fabricated via the open-source, license-free CORNERSTONE service, which can be accessed directly⁴¹ or via EUROPRACTICE⁴². The devices were built following the standard multi-project-wafer (MPW) process on the 220 nm silicon-on-insulator (SOI) platform comprising a 220 nm thick Si overlayer and a 2 µm thick buried oxide layer (BOX) ⁴³. All lithography processes were carried out via 248 nm deep-UV projection lithography on 200 mm wafers. First, grating couplers were patterned and etched 70 nm via an inductively coupled plasma (ICP) process based on SF₆ and C₄F₈ chemistry. Next, a low dose p-type doped layer was formed by ion implantation of boron. Note that in order to utilize the self-aligned process to ensure a repeatable pn-junction position within the waveguides ⁴⁴, the entire waveguide region of the device, which was defined later in the process flow, was implanted with boron. A 200 nm SiO₂ layer was then deposited by plasma-enhanced chemical vapor deposition (PECVD), which firstly acted as a hard mask for the subsequent rib waveguide etching step that left a 100 nm thick Si slab layer, and secondly used to protect the top of the waveguides from the ensuing n-type ion implantation process using phosphorus. During this n-type ion implantation step, the wafer was tilted 45° in order to move the pn junction into the waveguide to improve the resulting device modulation efficiency. Using this so-called self-aligned process, the junction position was defined by the implantation energy, and not by a lithographic process which would introduce a variable alignment error across the wafer. Furthermore, in order to ensure that all required waveguide sidewalls were implanted, irrespective of the sidewall orientation (e.g. in a u-shaped modulator), 6 separate implantation steps were performed, each with an additional 60° wafer rotation. Also note that the implantation dose was increased in order to compensate for the p-type doping that was earlier implanted into the waveguides. Following this, high dose p-type and n-type regions were formed by ion implantation for ohmic contacts, and the wafer was subsequently annealed in order to activate the doping. A 1 µm thick SiO₂ top cladding layer was then deposited by PECVD, into which vias were formed by ICP etching to expose the highly doped regions. A metal stack of Ti, TiN and Al was then sputtered, and finally the metal layer was etched by an ICP process to form electrodes.

II Photonics device modelling

Based on the process parameters (i.e., doping/implantation profile, anneal temperature, dimensions of PN junction and waveguide) adopted in the above photonics device, the phase shifter is modelled using SILVACO TCAD. The concentration distribution profile of electrons and holes under different DC bias voltages are simulated, from which the perturbation map of the refraction index under different DC voltages is obtained by applying plasma dispersion equations in MATLAB. The change in effective refractive index is then calculated with a mode solver also in MATLAB. For transient simulations, ideal voltage step-up and step-down functions were applied to the device and the concentration distribution profiles of electrons and holes were extracted at different time steps following the voltage change. This process was repeated for different voltage steps with the PN junction DC biased from 1V to 8V. The corresponding response of effective refractive index change was calculated again using MATLAB and the intrinsic bandwidth of the phase shifter calculated by using equation f_3dB = 0.35/τ_{delay ,} where τ_delay is the averaged time difference between 10% and 90% of the rising and falling edge of the effective refractive index step response, respectively. Furthermore, the conductance G and the capacitance C of the modelled area are also extracted, which are then merged with the RF loss profiles of the electrodes (from Keysight ADS) to estimate the electrical properties (i.e. characteristic impedance, effective index) of the phase shifter.

III Design of CMOS driver chip

When designing the electronic driver chip, the first step is to determine the characteristic impedance(Z0) of the CPW and the RF loss profile for different phase shifter lengths on the photonic chip. The characteristic impedance of the phase shifter is determined to be approx. 35–45 ohm when the PN junction is reverse biased from 1V to 8V. Hence the required far-end termination is determined to be a 39.5 ohm resistor in series with a 150pH inductor, the latter compensates the parasitic effects associated with the resistor and IO PADs. The RF loss profile of the phase shifters at different lengths are then imported into the Integrated Circuit (IC) design platform, in which the dimensions of inductive peaking (K1) and the value of near-end resistors (52 ohm) are determined by sweeping a range of values. The key values of the near-end and far-end terminations are highlighted in Fig. 2(a), with the dimensions of the T-coil peaking highlighted in Fig. 2(b). The standard cascaded current mode logic function is designed to generate switching currents (Iin+/Iin-), which can be sustained within the power supply range 1.5V-2.5V (i.e. no transistors will experience the risk of voltage break-down). A one-stage pre-driver is designed with inductive network (K2) to ensure that transistor M1 can fully switch on/off across the whole frequency band (up to 67GHz). A 50ohm input impedance matching network is designed to interface with an external signal source and provide the necessary DC biasing for the pre-driver. The whole schematic is shown in Fig. 2 (a), with the microscope view of the CMOS chip shown in Fig. 2(c). The whole electronic chip is then designed via a standard analogue/RF IC design flow (Cadence Virtuoso + Keysight ADS), in which the parasitic effects associated with all components, including I/O PADs, solder bumps etc., are appropriately modelled.

IV Integration of electronics and photonics

The CMOS chip was fabricated via a shared MPW run, where the choice of bonding pad was limited to standard wire-bonding PADs. Therefore, standard gold studs were first introduced on the surface of the CMOS PADs, with the diameter of the gold stud controlled at approx. 55um-60um. The CMOS chip was then flip-chip bonded onto the photonics chip via a thermal compression process, realized by using a flip-chip bonding machine (Finetech lambda). The 3D packaged module is then embedded within a bespoke designed PCB, which provides all power supplies and DC control signals. Al bonding wires were then used to electrically connect between the PCB and AL metals tracks on the photonics chip. Finally, gold-wire based air-bridge bonding was deployed on top of the CPW tracks of the photonic chip with the loop height controlled at about 150um and loop gap at about 250—300um.

V Device characterization

Two standalone MZMs (1.0mm and 2.0mm long) were characterized to extract fundamental process parameters (optical insertion loss and Vpi·L). The modulation efficiency (Vpi·L) is 1.9V·cm when operating at 6V reverse bias, while the optical insertion loss of the phase shifter is about 2.67dB/mm.

A Keysight 4-port Lightwave Component Analyzer (LCA) N4273E+N5227B was utilized to characterize the EO/EE response of all devices reported in this work. When conducting the EO response testing, the LCA is configured in differential mode, i.e. two electrical output ports and one optical input port. Therefore, the EO response results presented in Fig3(a-d) represent the ratio of optical response in respect to the electrical differential inputs. The power level of each electrical port is set at -12dBm, while the main power supply of the driver is set at the maximum operation point of 2.5V.

During eye-diagram testing, the reverse bias voltage of all the MZMs is set at 6V for consistency. The testing setup is shown in Fig3(e). The SHF bit pattern generator provides 4 independent PRBS11 code signals, two of which are fed into a 100G MUX (SHF C603B) to generate a pattern of length 2¹²-2 with a single-ended voltage swing of 0.5V and twice the data rate of each individual signal. The voltage swing generated from 100G MUX is then fed into the device under test (driver + MZM) via a 67GHz GSGSG probe. A Keysight 81606A provides a tunable light source, which is fed into the device via a grating coupler. Light after the output grating coupler was amplified by an erbium-doped fibre amplifier (EDFA LNA-150). The optical noise was suppressed using a 5nm wide bandpass filter (XTA-50/W) before being fed into a 70GHz photodetector (XPDV3120), which is directly coupled to the 80GHz electrical port of a Keysight Digital Communication Analyzer (Keysight Infiniium DCA-X 86100D with Agilent 86116C-040 plugin module + 86107A precision time base plugin module). The eye-diagram characterization is done by setting the DCA without any "smoothing", "averaging", or "DSP equalization".

VI Bit error rate testing

The BER testing uses "JITTER MODE" analysis in the DCA. To emulate the practical scenario at the receive side, during OOK testing, a half-baud rate filter (56GHz in this case) was applied together with 6-tap Feed Forward Equalization (FFE) during the BER testing, and the FFE coefficient was kept the same during power sweeping. Similarly, within the PAM-4 testing, a half-baud rate filter (50GHz and 56GHz for 200Gb/s PAM-4 and 224Gb/s PAM-4) was applied together with 12-tap FFE within the DCA.

As suggested by the technical support team of the DCA manufacturer (Keysight), the symbol error rate (SER) floor represents the BER performance of the received signal when operating at OOK mode. When it comes to the PAM-4 results, three SER floor results represent the BER results of the upper, middle and lower eyes. The aggregate BER of the PAM-4 waveforms is then calculated as BER = 1/2·BERupper + BERmid + 1/2·BERlow, which is consistent with previous work ³².

It should be highlighted that the results presented in this work are limited by the bandwidth of the available testing equipment, and hence it was only possible to conduct testing up to 112G baud and EO bandwidth results up to 67GHz. Theoretically, the bandwidth limit of our device should come from the self-resonant frequency of the peaking inductors utilized in the driver design, which is about 80GHz. Therefore, we strongly believe it is possible for our device to demonstrate 150-160G baud transmission if such high-speed testing equipment was available.

Acknowledgement

This work is supported by Engineering and Physical Sciences Research Council (EP/V012789/1, EP/N013247/1, EP/T019697/1, EP/L00044X/1). Ke Li acknowledges technique support from Keysight during the device characterization. Ke Li acknowledges the technique discussion from Prof. Fan Zhang, Peking University China, during the data transmission testing. David J. Thomson acknowledges funding from the Royal Society for his University Research Fellowship.

Author contribution

KL conceived idea and lead the research. GTR supervised the project and manage the silicon photonics group. KL modelled and designed the electronics devices. DJT, SL, WC, KL modelled and designed the photonics device. DJT, XY, CGL, MB, WZ, ME, DT, HD conducted the photonics device fabrication. KL conducted E-O integration process. KL, WZ and WC conducted the device characterization and data transmission testing. KL and FM designed the PCB. WC took photos for the fully packaged devices and KL composed 3D images. KL analyzed the data and co-wrote the manuscript with DJT, CGL and GTR. All authors commented on the manuscript.

Competing interests

The authors declare no competing interests.

Additional information

Extended data is available for this paper at https://doi.org/10.5258/SOTON/D2331

Correspondence and requests for materials should be addressed to KL, DJT and GTR.

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There is NO Competing Interest.

OOKtesting1.mp4
Testing_video_OOK
PAM4testing1.mp4
Testing_video_PAM-4

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112G baud sub pJ/bit integrated CMOS-silicon photonics transmitter

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