Aligned carbon nanotube integrated circuit downsizing toward a sub-10 nm node

doi:10.21203/rs.3.rs-2000386/v1

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Aligned carbon nanotube integrated circuit downsizing toward a sub-10 nm node

https://doi.org/10.21203/rs.3.rs-2000386/v1

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published 17 Jul, 2023

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Transistors on aligned semiconducting carbon nanotubes (A-CNTs) have been considered a promising substitute for mainstream Si transistors to extend integrated circuit (IC) technology owing to their potential advantages of easy miniaturization and high energy efficiency, but whether A-CNT FETs can be scalably fabricated with ultrascaled whole dimensions while maintaining high performance remains questionable. Here, we explore the whole size scaling down potential of A-CNT transistors and demonstrate the possibility of implementing such small-geometry transistors in ultra-large-scale ICs that consist of billions of transistors. A-CNT transistors with a contacted gate pitch (CGP) of 175 nm have been achieved by simultaneously scaling the gate length and the contact length, and exhibit an on-current of 2.24 mA/μm and a peak transconductance of 1.64 mS/μm, surpassing silicon 45 nm node transistors in terms of both size and electronic performance. A static random-access memory (SRAM) cell has been built using six A-CNT transistors in an area of 0.967 μm2, which is comparable to the commercial silicon 90 nm technology node and is the smallest SRAM cell based on non-Si semiconductors. Furthermore, a full-contact structure is introduced between the metal and A-CNTs to achieve a contact resistance as low as 90 Ω·μm and to reduce the dependence on the contact length. A-CNT transistors downsized to a CGP of 55 nm (corresponding to the silicon 10 nm technology node) have been demonstrated to outperform 10 nm Si MOS transistors in terms of carrier mobility and Fermi velocity, indicating the tremendous potential of A-CNT transistors in high-performance digital ICs of sub 10 nm nodes.

Development of integrated circuits (ICs) has been accomplished by downsizing silicon complementary metal-oxide-semiconductor (CMOS) transistors to improve the performance, integration density and parallel operation capability and simultaneously decrease the power consumption and cost. As sub-5 nm node Si CMOS technology is used for commercially available ultra-large-scale ICs (ULSICs), the downsizing of Si transistors is reaching the limit set by the power dissipation, cost and even physics ¹. Emerging IC technologies with novelties in materials, device structures/mechanisms, and system architectures have been intensively explored in academia and industry to meet the ever-increasing computing demands ^2-5. One of the most promising methods is to use semiconductors with an ultrathin body and a high carrier mobility as active channels to construct field-effect transistors (FETs) with a better scaling down property and higher performance than Si transistors, which provides significant improvement in performance and integration density for future digital IC applications ^6-8. Therefore, tremendous FETs and simple ICs have been demonstrated with one-dimensional (1D) materials, such as semiconducting nanowires and carbon nanotubes (CNTs), and two-dimensional (2D) materials, such as transition metal dichalcogenides (TMDs) and black phosphorus (BP) ^3,9-17. Among these new semiconductors, semiconducting CNTs have attracted long-term and tremendous attention owing to their unique geometric configuration and outstanding electronic properties ^18-20. High and symmetric performance CMOS FETs have been demonstrated with individual CNTs through a doping-free process down to a sub-10 nm gate length ²¹ and have shown excellent scaling down behavior and extraordinary electronic performance surpassing that of silicon CMOS transistors, indicating the great potential of CNT electronics in future digital ICs. However, these advantages were only demonstrated for individual-CNT-based transistors ^22-24, which cannot be scalably fabricated as building blocks for ULSIs. The recent improvements in the semiconducting purity and alignment of CNT materials enable scalable fabrication of CNT transistors ^16,25-30, and FETs with practical performance comparable to that of Si transistors have been fabricated with scaled gate length (L_g) from aligned semiconducting CNTs (A-CNTs) ^13,14,16. However, fabricated with a large contact length (L_con, usually above 200 nm) ^14,16, the contacted gate pitch (CGP), a key featured dimension reflecting the integration density of transistors in one generation ³¹, of these devices is too large to promise the scaling potential of CNT electronics. A-CNT FETs with a 40 nm footprint have been reported by using end-bonded contact with L_con down to 10 nm ^15,32, but the transistors are based on a back-gated structure, and there is no obvious performance advantage with respect to the corresponding Si p-type FETs. Furthermore, various ICs, including modern microprocessors consisting of more than 14,000 transistors, have been realized ^17,33-41, but the low performance and large circuit area induced by the large CGP of CNT FETs completely deviate from the predicted advantages of CNT electronics. In each generation of Si CMOS technology, the area of a six-transistor (6T) static random-access memory (SRAM) cell has also been used as an important figure-of-merit to benchmark practical integration density ⁴². The reported area of CNT-based SRAM cells thus far is in the range of 2,000 to 100,000 μm² ^26,43, which is at least 2,000 times larger than that of 90 nm node Si CMOS technology (1 μm²) ⁴⁴. Since a combination of high performance and ultrascaled whole size is necessary for transistors to construct modern digital ICs, whether A-CNT FETs can be scalably fabricated with ultrascaled whole dimensions while maintaining high performance remains questionable, which is also a common problem existing for all low-dimensional semiconductor-based FETs. Exploring the performance advantage over mainstream IC technology under a constrained CGP to draw up an available roadmap for industrial development of A-CNT transistors and digital ICs is highly desirable.

In this work, we explore the possibility of implementing high-performance and small-geometry A-CNT FETs in ULSIs that consist of billions of transistors. A-CNT FETs with a small CGP and high performance are explored to target the 45 nm to 90 nm node Si technology. A-CNT 6-T SRAM cells are placed within an area of 1 μm², which is comparable to the commercial silicon 90 nm technology node and is the smallest SRAM cell based on non-Si semiconductors. We also scale down L_con through a full-contact structure between the metal and A-CNTs and explore the feasibility and potential of sub-10 nm node A-CNT transistors.

The CGP, defined as the smallest possible distance between gates of adjacent transistors, is used to characterize the integration density in Si CMOS technology nodes ³¹ and is also known as the contacted poly pitch (CPP). As shown in Figure 1a, the CGP of a transistor equals the sum of L_g, L_con, and two times the spacer length (L_sp) and is a more accurate figure-of-merit than L_g to reflect the true scaling capability ⁴². Therefore, the whole downsizing of transistors in ICs involves shrinking not only L_g but also L_con, which affects the contact resistance (R_c) but is usually ignored by many scientific studies ^13,14,16,40. Top-gated FETs with scaled CGP were fabricated on an A-CNT monolayer with a density of approximately 300 CNT/μm and a diameter distribution of 1.514 ± 0.076 nm (see the transmission electron microscopy (TEM) and scanning electron microscopy (SEM) images in Fig. 1b) to form good ohmic contacts ^45,46. Typical FETs with a CGP of 175 nm (see the SEM image in Fig. 1c) were achieved with an L_con of 80 nm, an L_sp of 5 nm (actually the thickness of the gate insulator) and an L_g of 85 nm, corresponding to the CGP of 90 nm (260 nm) to 45 nm (160 nm) nodes in Si CMOS technologies. With Pd as source/drain contacts, the transistors present p-type field-effect characteristics (Fig. 1d and e) with high performance, including a current on/off ratio (I_on/I_off) of 10⁵, a subthreshold swing (SS) of 178 mV/dec and a threshold voltage (V_th) of -0.67 V at a low bias (V_ds = -0.1 V), a saturation current (I_on) of 2.24 mA/μm (V_ds = -0.8 V) and a peak transconductance g_m of 1.64 mS/μm (see Figure S1 in the Supplementary Information). Notably, the FET still exhibits good ohmic contact with a total resistance of 240 Ω·μm (V_gs = -2.2 V) even when L_con is scaled down to 80 nm. As a direct comparison, an adjacent FET (see Figure S1 in the Supplementary Information) with longer L_con (200 nm) presented improved I_on (2.79 mA/μm) and g_m (2.06 mS/μm) and a lower total resistance of 220 Ω·μm (V_gs = -2.2 V). Therefore, the 175 nm CGP A-CNT FET outperforms the silicon 45 nm technology node (CGP = 160 nm) in terms of I_on and g_m, demonstrating the performance superiority of CNT-based electronics at similar integration densities. However, the SS is as high as 178 mV/dec in the A-CNT FET and is much larger than that of commercial Si MOS FETs (<80 mV/dec). The high SS mainly originates from the disorder in the CNT array and the high density of interface states in the gate stack. Tubes in the high-density A-CNT array easily stack onto each other during the fabrication process, which destroys the monolayer nature of A-CNTs and leads to nanotube pitch variations (Figure S2 in the Supplementary Information). The stacking will severely degrade the gate efficiency owing to the intertube electrostatic screening effect. Moreover, a density of interface states as high as 10¹³ cm^-2eV^-1 (see Figure S3 in the Supplementary Information) lowers not only the on-state performance but also the switching-off property ^16,47. Future improvements, such as keeping the monolayer morphology in the fabrication process and lowering the interface state density in the gate stack, are expected to greatly lower the SS to an ideal value and further improve the performance of A-CNT FETs while maintaining a small CGP, which will provide promising building blocks for high-speed ULSIs.

In mainstream Si technology, the area of an SRAM cell is generally used as an important figure-of-merit to benchmark the integration density of a certain technology node ^44,48-56. We designed and fabricated scaled SRAM cells consisting of six whole-size-scaled p-type A-CNT FETs (see the circuit diagram and layout in Figure 2a-b and Figure S4). The SRAM cells consisting of six A-CNT FETs with a CGP of 420 nm (see Fig. S4 in the Supplementary Information, L_con = 250 nm, L_g = 150 nm) present a total area of 8.58 μm², which is similar to that (5.59 μm²) of the silicon 0.18 μm technology node ⁵⁰. With scaling of the A-CNT FETs to a CGP of 175 nm, the area of the 6T-SRAM cells is scaled down to 0.976 μm², as shown in Fig. 2b, while maintaining a normal function at V_dd = 1.0 V, as shown in Fig. 2c and 2d. Significantly, this is the first demonstration of SRAM cells with a total area below 1 μm² based on all non-Si semiconductor technology, even without complex multilayer back-end interconnects, indicating the downsizing advantage of CNT electronics. The main advantage of A-CNT FET technology in terms of integration density originates from the isolation region. Specifically, Si CMOS technology at 130-45 nm nodes employs shallow trench isolation (STI) with a pitch of approximately 200 nm ^44,51,52, while a simple isolation method, such as cutting the CNT array, is adequate in A-CNT FET technology, which leads to a significantly smaller isolation region. If the 175 nm CGP A-CNT FETs demonstrated here are defined as a generation technology node (90 nm) for CNT electronics, then the key pitch comparison between the CNT 90 nm node and 3 generations (130 nm, 90 nm and 45 nm) of Si technology is shown in Fig. 2e and f. The CNT 90 nm node technology corresponds to the Si 0.13 μm technology node in terms of L_g (70 nm), to the Si 90 nm node in terms of the SRAM cell total area (~1 μm²), and to the Si 45 nm node in terms of the CGP (160 nm) but exceeds all of them in performance owing to the intrinsic advantage of the material. Although they exhibit the same SRAM cell area as and a higher integration density than the silicon 90 nm technology node, the 90 nm node CNT FETs have a larger L_g (85 nm vs. 50 nm), indicating a relaxed manufacturing accuracy requirement in CNT electronics at the same node. As a result, the 175 nm CGP A-CNT FET technology can comprehensively outperform the Si 90 nm node technology in terms of both integration density and performance. If CNT CMOS FET technology is developed and incorporated with a mature back-end copper interconnect process, then the 175 nm CGP A-CNT FET technology will be comparable to or even exceed the Si 45 nm node technology in terms of both the integration density and performance.

Realization of A-CNT/metal contact with both low contact resistance and small size is necessary for whole downsizing of A-CNT transistors, especially down to a 50 nm CGP (sub 10 nm node). Two kinds of contact structures are widely used in low-dimensional semiconductor FETs, i.e., side contact and end contact (named end-bonded contact or edge contact) ⁵⁷. The side-contact structure is widely used and adopted by our above transistors since this structure is easy to fabricate. However, its contact resistance strongly depends on the contact length ^58,59. The end-contact structure is almost independent of the contact length but suffers from high contact resistance and complicated processes, including high-temperature annealing ^15,32. Here, we utilized a full-contact structure to realize high-quality and small-size contact in A-CNT FETs (Figure 3a). The transfer length method (TLM) was used to extract the contact length (L_con)-dependent contact resistance (R_c) of the two kinds of contact structures from top-gated A-CNT FETs. Specifically, a group of top-gated A-CNT FETs with a fixed L_con but various L_g from several tens to hundreds of nm were fabricated (see the SEM image in Fig. 3b) and used to retrieve the contact resistance for this fixed L_con (see the details in Methods and the measured electronic performances of all FETs in Figures S5 and S6 in the Supplementary Information). Typical transfer characteristics of the two groups of A-CNT FETs with side contact (L_con of 80 nm) and full contact (L_con of 30 nm) are shown in Fig. 3c and 3d, respectively, both indicating high-performance p-type FET characteristics as well as a current on/off ratio up to 10⁵. The L_g-dependent R_tot data were then retrieved from the FETs with side- and full-contact structures for various L_con values, as shown in Fig. 3e and 3f, respectively. The R_totvalues of full-contact FETs are obviously lower than those of side-contact FETs at the same drain and gate bias (Fig. 3g), which benefits from the lower R_c originating from the use of the full-contact structure (Fig.3h). Notably, the full-contact structure presents comprehensively lower and weaker L_con-dependent contact resistance than the side-contact structure since the transfer length is 60 nm and 80 nm for full and side contacts, respectively (see Figure S7 in the Supplementary Information). By adopting the full-contact structure, the R_c of A-CNT FETs can be lowered to 163 Ω·μm and maintained at approximately 200 Ω·μm even at an L_con scaled down to 30 nm, which lays the foundation for whole size miniaturization of high-performance A-CNT FETs. The full-contact structure combines the carrier injection mechanism of side contact and end contact, i.e., the carriers can be injected from the metal to CNTs at the side (length-dependent) and at the edge (length-independent). Therefore, the full-contact A-CNT/metal junction exhibits lower contact resistance than the side-contact or end-contact junctions while maintaining a weaker contact length dependence⁵⁷. Furthermore, the full-contact A-CNT FET-based ICs present advantages in whole downsizing over Si CMOS ICs arising from the small isolation region, as shown in Fig. 3a. Compared with STI, which requires a complex process and a large area cost ⁶⁰, the isolation between CNT FETs only requires one-step oxygen plasma etching to remove unwanted CNTs in the isolation area.

We further scaled the gate length down to 30 nm to explore the CGP scaling down potential of full-contact A-CNT FETs. Figure 4a demonstrates that the isolation spacing between two FETs can be scaled to 32 nm, which is much smaller than the STI region (~200 nm) in Si ICs ^44,51,52. The A-CNT FETs with scaled L_g while maintaining a long contact length (L_con of 200 nm, as shown in Fig. 4a) exhibit E-mode p-type behavior (V_th = -0.34 V at V_ds = -0.1 V) with an on/off ratio of ~10³ at a V_ds of -0.7 V (Fig. 4b). A minimum total resistance R_tot as low as 186 Ω·μm (Fig. 4c and Figure S8 in the Supplementary Information) was achieved, indicating that R_c is lowered to approximately 90 Ω·μm, benefitting from the 200 nm L_con full contacts. More importantly, the FET presents high performance, including peak g_m of 2.69 mS/μm and I_on of 3.31 mA/μm (Fig. 4c and Fig. S8 in the Supplementary Information) at a drain-to-source bias of -0.7 V, which represents the record performance thus far for CNT-based FETs ^13,14,16. Since the 30 nm gate length A-CNT FETs have a higher current driving capability at smaller V_ds than the 10 nm node (L_g = 18 nm) Si transistors (Fig. 4c), there is sufficient room for performance compromise to realize a 10 nm node (~ 54 nm CGP) CNT FET with a 30 nm L_g through scaling of the contact length. L_con was then aggressively shrunk to 15 nm while keeping a 30 nm L_g, and then, the FETs were designed with a CGP of 55 nm (L_sp=5 nm). The as-fabricated A-CNT FET (see the SEM image and cross-sectional TEM image in Fig. 4d) exhibits an as-fabricated L_g of 35 nm and an as-fabricated actual L_con of approximately 20 nm (16 nm/27 nm for the source/drain) owing to process variations, indicating a practical minimum CGP of 61 nm. The transistor presents high performance (Fig. 4e and Fig. S8 in the Supplementary Information), including an I_on of 2.43 mA/μm and a g_m of 2.45 mS/μm at a V_ds of -0.8 V, which is still comparable to that of the 10 nm node Si PMOS FET ⁵⁶, although slightly lower than that of the 200 nm contact length transistor in Fig. 4b. However, fabrication of sub-55 nm CGP A-CNT FETs with both small gate length and full-contact length requires a double self-aligned (self-aligned gate and self-aligned contact) process, as proposed in Fig. S9 (see the detailed in the Supplementary Information).

To estimate the latent capacity of A-CNT FETs as a promising candidate for Si transistors in digital ICs, we benchmarked the performance of A-CNT FETs with that of silicon CMOS transistors at various CGPs (as shown in Figure 5a and Figures S10 and S11 in the Supplementary Information). At CGPs larger than 160 nm (corresponding to a 90 nm node), the A-CNT FETs present much higher I_on and g_m than the Si transistors. The performance advantage of A-CNT FETs over Si MOS FETs reaches the maximum value at the 90 nm node since a sufficiently long contact length can be used in A-CNT FETs, indicating that the 90 nm node is the most worthwhile technology node for the application of CNT ICs at the current stage. Shrinking the A-CNT FETs to generations below 45 nm requires a novel contact structure to scale the contact length and CGP while maintaining high performance. By introducing full contacts instead of side contacts, the CGP of A-CNT FETs has been demonstrated to be scaled down to approximately 61 nm (at L_g=30 nm, limited by the accuracy of e-beam lithography and the thickness of the gate oxide), with performance superior to that of the corresponding node Si transistors. In principle, the CGP can be further scaled to below 40 nm by scaling L_g down to approximately 15 nm, which will contribute to the performance increase. Therefore, with downsizing to a sub-10 nm node (CGP < 50 nm), A-CNT FETs with current material and device technologies will retain an obvious performance advantage over commercial Si technology, indicating the great potential of CNT electronics for digital ICs. The performance advantage of A-CNT transistors mainly originates from the high carrier mobility and Fermi velocity in the A-CNT array, as shown in Fig. S13 and Fig. 5b. The effective carrier mobility retrieved from our A-CNT FETs reaches 1500 cm²/Vs at an L_g of 3 μm and 500 cm²/Vs even at an L_g of 30 nm (see Figure S12 in the Supplementary Information) and is at least four times higher than the electron/hole mobility of Si transistors at any gate length ^5,61,62. The A-CNT FETs have a much higher injection velocity (see the details in Method and Figure S13 in the Supplementary Information) than the Si transistors (either NMOS or PMOS) at any gate length. Furthermore, the injection velocity in A-CNT FETs increases with scaling down of L_g following an inversely proportional relation even to an L_g of 30 nm, which indicates that the performance advantage over Si transistors will further increase at the sub-10 nm node ⁶³. Notably, although the injection velocity in 30 nm L_g A-CNT FETs reaches 1.1×10⁷cm/s, it is still lower than that (3×10⁷ cm/s) in individual-CNT-based FETs ⁶², indicating that there is great room to improve the performance of A-CNT FETs.

Off-state current I_off is one of the metrics of most concern for transistors, as it directly affects the statistical power dissipation in digital ICs and requires more attention in A-CNT FETs, which are subject to gate-induced drain leakage (GIDL) ^64,65 mainly owing to the small bandgap of CNTs. We compared A-CNT FETs with commercial Si FETs from the 130 nm to 32 nm node in the I_on-I_off representation (Fig. 5c). The 175 nm CGP A-CNT FETs in this work show an obvious advantage in terms of I_on versus I_off over Si PMOS FETs, i.e., achieving higher I_on than Si transistors under the same I_off, which verifies the advantage of the energy-delay product of CNT transistors. As L_g is scaled down to 30 nm, the I_off of A-CNT FETs drastically increases owing to GIDL, and some structural improvements are required to lower the field strength of the drain to suppress I_off^65-69.

In summary, we explore the whole size scaling down potential of A-CNT FETs and demonstrate scaled A-CNT FETs with a CGP of 175 nm and 6-T SRAM cells within an area of 1 μm². Furthermore, a full-contact structure is introduced to lower the contact resistance, reduce the contact length, and enable the A-CNT FETs to shrink to a CGP below 50 nm (corresponding to a 10 nm technology node) while outperforming 10 nm Si PMOS transistors owing to the higher carrier mobility and Fermi velocity. The performance advantage provides the A-CNT FETs with more room for the trade-off between the gate length and contact length for whole downsizing, indicating the tremendous potential of A-CNT transistors in high-performance digital ICs containing tens of billions of transistors. However, several challenges remain for CNT transistor applications in digital ICs. First, n-type FETs should be developed with performance and CGP matching those of p-type FETs to constitute CMOS technology. Second, a high-quality gate dielectric with an ultrathin equivalent oxide thickness (EOT) and a low interface state density should be realized on A-CNTs to further improve the gate efficiency, which is predicted to improve the performance and lower the SS. Finally, a well-designed device structure at the drain side is necessary to suppress GIDL and lower the static power dissipation.

1 Haensch, W. et al. Silicon CMOS devices beyond scaling. IBM Journal of Research and Development 50, 339-361 (2006).

2 Bae, W. Today’s computing challenges: opportunities for computer hardware design. PeerJ Computer Science 7 (2021).

3 Liu, C. et al. Two-dimensional materials for next-generation computing technologies. Nat. Nanotechnol. 15, 545-557 (2020).

4 Leiserson, C. E. et al. There’s plenty of room at the Top: What will drive computer performance after Moore’s law? Science 368, eaam9744 (2020).

5 The International Roadmap For Devices And Systems, https://irds.ieee.org/editions/2020 (2020).

6 Cavin, R. K., Lugli, P. & Zhirnov, V. V. Science and Engineering Beyond Moore's Law. Proceedings of the IEEE 100, 1720-1749 (2012).

7 Akinwande, D. et al. Graphene and two-dimensional materials for silicon technology. Nature 573, 507-518 (2019).

8 Cao, Q. Carbon nanotube transistor technology for More-Moore scaling. Nano Research 14, 3051-3069 (2021).

9 Liu, L. et al. Uniform nucleation and epitaxy of bilayer molybdenum disulfide on sapphire. Nature 605, 69-75 (2022).

10 Wu, Z. et al. Large-scale growth of few-layer two-dimensional black phosphorus. Nature Materials 20, 1203-1209 (2021).

11 Shen, P.-C. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211-217 (2021).

12 Sun, Y., Dong, T. G., Yu, L. W., Xu, J. & Chen, K. J. Planar Growth, Integration, and Applications of Semiconducting Nanowires. Advanced Materials 32 (2020).

13 Lin, Y. et al. Enhancement‐Mode Field‐Effect Transistors and High‐Speed Integrated Circuits Based on Aligned Carbon Nanotube Films. Advanced Functional Materials 32, 2104539 (2021).

14 Shi, H. et al. Radiofrequency transistors based on aligned carbon nanotube arrays. Nature Electronics 4, 405-415 (2021).

15 Cao, Q., Tersoff, J., Farmer, D. B., Zhu, Y. & Han, S.-J. Carbon nanotube transistors scaled to a 40-nanometer footprint. Science 356, 1369-1372 (2017).

16 Liu, L. et al. Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics. Science 368, 850-856 (2020).

17 Shulaker, M. M. et al. Carbon nanotube computer. Nature 501, 526-530 (2013).

18 Franklin, A. D. Nanomaterials in transistors: From high-performance to thin-film applications. Science 349, aab2750-aab2750 (2015).

19 Franklin, A. D. The road to carbon nanotube transistors. Nature 498, 443-444 (2013).

20 Avouris, P., Chen, Z. & Perebeinos, V. Carbon-based electronics. Nature Nanotechnology 2, 605-615 (2007).

21 Qiu, C. et al. Scaling carbon nanotube complementary transistors to 5-nm gate lengths. Science 355, 271-276 (2017).

22 Bachtold, A. Logic Circuits with Carbon Nanotube Transistors. Science 294, 1317-1320 (2001).

23 Javey, A., Guo, J., Wang, Q., Lundstrom, M. & Dai, H. Ballistic carbon nanotube field-effect transistors. Nature 424, 654-657 (2003).

24 Zhang, Z. et al. Self-Aligned Ballistic n-Type Single-Walled Carbon Nanotube Field-Effect Transistors with Adjustable Threshold Voltage. Nano Lett 8, 3696-3701 (2008).

25 Zhao, M. et al. DNA-directed nanofabrication of high-performance carbon nanotube field-effect transistors. Science 368, 878-881 (2020).

26 Geier, M. L. et al. Solution-processed carbon nanotube thin-film complementary static random access memory. Nature Nanotechnology 10, 944-948 (2015).

27 Shulaker, M. M. et al. High-Performance Carbon Nanotube Field-Effect Transistors. IEEE International Electron Devices Meeting (2014).

28 Brady, G. J. et al. Polyfluorene-Sorted, Carbon Nanotube Array Field-Effect Transistors with Increased Current Density and High On/Off Ratio. ACS Nano 8, 11614-11621 (2014).

29 Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nat. Nanotechnol. 8, 180-186 (2013).

30 Park, H. et al. High-density integration of carbon nanotubes via chemical self-assembly. Nat. Nanotechnol. 7, 787-791 (2012).

31 Datta, S. Ten nanometre CMOS logic technology. Nature Electronics 1, 500-501 (2018).

32 Cao, Q. et al. End-bonded contacts for carbon nanotube transistors with low, size-independent resistance. Science 350, 68-72 (2015).

33 Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74-78 (2017).

34 Kanhaiya, P. S., Lau, C., Hills, G., Bishop, M. D. & Shulaker, M. M. Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells. IEEE Transactions on Electron Devices 66, 5375-5380 (2019).

35 Yang, Y., Ding, L., Han, J., Zhang, Z. & Peng, L.-M. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films. ACS Nano 11, 4124-4132 (2017).

36 Hills, G. et al. Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595-602 (2019).

37 Chen, B. et al. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits. Nano Lett 16, 5120-5128 (2016).

38 Zhong, D. et al. Gigahertz integrated circuits based on carbon nanotube films. Nature Electronics 1, 40-45 (2018).

39 Han, S.-J. et al. High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes. Nature Nanotechnology 12, 861-865 (2017).

40 Cao, Y. et al. Radio Frequency Transistors Using Aligned Semiconducting Carbon Nanotubes with Current-Gain Cutoff Frequency and Maximum Oscillation Frequency Simultaneously Greater than 70 GHz. ACS Nano 10, 6782-6790 (2016).

41 Liu, L. et al. Carbon Nanotube Complementary Gigahertz Integrated Circuits and Their Applications on Wireless Sensor Interface Systems. Acs Nano 13, 2526-2535 (2019).

42 Samavedam, S. B. et al. Future Logic Scaling: Towards Atomic Channels and Deconstructed Chips. International Electron Devices Meeting (IEDM) (2020).

43 Zhu, M. G., Zhang, Z. & Peng, L. M. High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory. Adv. Electron. Mater. 5, 1900313 (2019).

44 Ghani, T. et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. IEEE International Electron Devices Meeting 11.16. 11-11.16. 13 (2003).

45 Kim, W. et al. Electrical contacts to carbon nanotubes down to 1 nm in diameter. Applied Physics Letters 87, 173101 (2005).

46 Tulevski, G. S. et al. Toward high-performance digital logic technology with carbon nanotubes. ACS nano 8, 8730-8745 (2014).

47 Xu, L., Gao, N., Zhang, Z. & Peng, L.-M. Lowering interface state density in carbon nanotube thin film transistors through using stacked Y₂O₃/HfO₂ gate dielectric. Appl Phys Lett 113, 083105 (2018).

48 Bohr, M. et al. A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation. IEEE International Electron Devices Meeting. 273-276 (1994).

49 Brand, A. et al. Intel’s 0.25 micron, 2.0 volts logic process technology. Intel Technology Journal Q 3, 1998 (1998).

50 Yang, S. et al. A high performance 180 nm generation logic technology. International Electron Devices Meeting, 197-200 (1998).

51 Tyagi, S. et al. A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects. International Electron Devices Meeting. 567-570 (2000).

52 Mistry, K. et al. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging. IEEE International Electron Devices Meeting. 247-250 (2007).

53 Natarajan, S. et al. A 32nm logic technology featuring 2 nd-generation high-k+ metal-gate transistors, enhanced channel strain and 0.171 μm² SRAM cell size in a 291Mb array. IEEE International Electron Devices Meeting. 1-3 (2008).

54 Auth, C. et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. symposium on VLSI technology (VLSIT). 131-132 (2012).

55 Natarajan, S. et al. A 14nm logic technology featuring 2 nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm²sram cell size. IEEE International Electron Devices Meeting. 3.7. 1-3.7. 3 (2014).

56 Auth, C. et al. A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects. IEEE International Electron Devices Meeting (IEDM). 29.21. 21-29.21. 24 (2017).

57 Allain, A., Kang, J., Banerjee, K. & Kis, A. Electrical contacts to two-dimensional semiconductors. Nature Materials 14, 1195-1205 (2015).

58 Franklin, A. D. & Chen, Z. Length scaling of carbon nanotube transistors. Nat Nanotechnol 5, 858-862 (2010).

59 Liu, L. et al. Scaling down contact length in complementary carbon nanotube field-effect transistors. Nanoscale 9, 9615-9621 (2017).

60 Nandakumar, M. et al. Shallow trench isolation for advanced ULSI CMOS technologies. International Electron Devices Meeting (1998).

61 Thompson, S. E. et al. A 90-nm logic technology featuring strained-silicon. IEEE Transactions on Electron Devices 51, 1790-1797 (2004).

62 Xu, L., Qiu, C., Zhao, C., Zhang, Z. & Peng, L.-M. Insight Into Ballisticity of Room-Temperature Carrier Transport in Carbon Nanotube Field-Effect Transistors. IEEE Transactions on Electron Devices 66, 3535-3540 (2019).

63 Del Alamo, J. A. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317-323 (2011).

64 Martel, R. et al. Ambipolar Electrical Transport in Semiconducting Single-Wall Carbon Nanotubes. Physical Review Letters 87 (2001).

65 Xu, L., Qiu, C., Peng, L.-M. & Zhang, Z. Suppression of leakage current in carbon nanotube field-effect transistors. Nano Research 14, 976-981 (2021).

66 Zhao, C. et al. Strengthened Complementary Metal–Oxide–Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application. ACS Nano 14, 15267-15275 (2020).

67 Srimani, T. et al. Asymmetric gating for reducing leakage current in carbon nanotube field-effect transistors. Appl Phys Lett 115, 063107 (2019).

68 Liu, L., Zhao, C., Ding, L., Peng, L. & Zhang, Z. Drain-engineered carbon-nanotube-film field-effect transistors with high performance and ultra-low current leakage. Nano Research 13, 1875–1881 (2019).

69 Qiu, C. G. et al. Carbon Nanotube Feedback-Gate Field-Effect Transistor: Suppressing Current Leakage and Increasing On/Off Ratio. ACS Nano 9, 969-977 (2015).

Acknowledgments

This work is supported by the Beijing Municipal Science and Technology Commission (Grant No. Z191100007019001-3) and Natural Science Foundation of China (62225101 and U21A6004).

Author contributions:

Z. Z. and L. M. P. proposed and supervised the project. Y. L. fabricated the scaled A-CNT FETs and 6T-SRAM cells. Y. L. and Y. C. characterized the devices and 6T-SRAM cells. L. X. extracted the mobility and injection velocity of the CNTs using the VS model. S. D. and C. J. performed the TEM characterizations. C. L. and Q. H. helped characterize the devices. Y. L., Y. C., Z. Z., and L. M. P. analyzed the data and wrote the manuscript. All authors discussed the results and commented on the manuscript.

Additional information

Correspondence and requests for materials should be addressed to (Z.Z.) [email protected].

Competing financial interests:

The authors declare no competing financial interests.

Data availability:

The data that support the plots within this paper are available from the corresponding author upon reasonable request.

There is NO Competing Interest.

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