A novel approach called Keeper in LEakage Control Transistor (KLECTOR) is presented in this paper to reduce leakage currents in SRAM architecture. The SRAM is significantly affected by the leakage current during the "standby mode", which is caused by the fabric which has a lower threshold voltage. KLECTOR circuit employs less power consumption by restricting the flow of current through devices of less voltage drops and relies heavily on the self-controlled transistor at the output node. It has been found from the presented results that static (leakage) power in the write operation is reduced to 63% and 69 % for the read operation. This proposed approach is designed and simulated using the Virtuoso, Cadence EDA tool.