The evaluation of the wireless channel linking a transmitter and a receiver is essential in many applications. In receiver design, channel estimate is a fundamental and difficult problem. A recent mathematical theory called compressive sensing (CS) makes use of the idea of randomness in the signal to recover sparse or compressible signals. This research work also proposes an efficient channel estimator with interference detection architecture for Multiple Input Multiple Output- Orthogonal Frequency Division Multiplexing (MIMO - OFDM) method. The proposed interference finding architecture efficiently detects and removes the interference between received signals with low power consumption and current consumption with minimum hardware requirements. The power consumption and latency for Virtex Family devices are 19mW and 9 ns respectively. The channel estimator with interference detection architecture is used to achieve the power consumption and latency (CPLD Family devices) are 21.97 and 10.32.
Research Article
Performance Analysis of Channel Estimator with Interference Detection Architecture
https://doi.org/10.21203/rs.3.rs-2369727/v1
This work is licensed under a CC BY 4.0 License
You are reading this latest preprint version
Channel
signals
MIMO
OFDM
power consumption
This work proposes an efficient channel estimator with interference detection architecture for MIMO-OFDM system. For an area-efficient design, Kalaivani et al. (2015) [1] created a minimum power circuit for an Orthogonal Frequency Division Multiplexing (OFDM) method. They achieved 1053 slices as their planned design when using the Single Delay Feedback (SDF) technique to lower the power dissipation of the Fast Fourier Transform (FFT) process. A low power OFDM system was developed by Isael Diaz et al. (2015) as a receiver module for use in Wireless Local Area Networks (WLAN). The authors used 0.18 m CMOS technology to accomplish 239K gates and 36 mW of power consumption. Ouyanget al. (2012) [2] used discrete Hartley transform in OFDM system to reduce its peak power consumption. The authors analyzed various intrinsic relationships between their proposed transform design and conventional FFT transformations.
The following ideas are observed from the conventional approaches of OFDM system design,
-
Conventional methods consume more power.
-
Latency of the conventional OFDM system is high.
-
Current consumption and Hardware Utilization are also high in conventional designs.
When the channel is in deep fading, the Mean Square Error Evaluation (MSE) in Least Square (LS) is high susceptible to unwanted signal (noise). But LS leverage's versatility comes from how easily it may be applied. A weight matrix added to LS can eventually produce Minimum MSE (MMSE), enhancing the efficiency of the OFDM system. Though more sub-carriers result in a more computationally intensive MMSE, they reduce fading. MMSE is widely thought to be superior to LS despite having a larger computational cost. Decision Directed Channel Estimation (DDCE) can perform better when gradual and flat fading are assumed. (Bölcskei & Paulraj 2000, Lu &2. Wang Xueyuan 2018) [3].
DDCE tracks the channel variation using the detected symbol feedback. The integrity of the last recognised symbol affects how well the DDCE method performs. Any divergence causes the inaccuracy to spread to successive estimations, which lowers performance. Additionally, performance loss occurs more frequently in fast fading scenarios. In fast fading environments, OFDM systems lose their orthogonality. Inter Carrier Interference results from intentional lack of orthogonality (ICI). The consequences of ICI limiting the use of one tap equalisers. Accurate assessment of the channel frequency response is necessary for compensating the impacts of ICI. Despite the fact that many studies have been conducted, the majority of them are obtained under constrained channel conditions. (Liu et al. 2001, Zhang et al .2017) [4]. A method for channel estimate in Long Term Evolution (LTE) downlink networks was put out by Darshan Bharwad et al. (2015). It was suggested to use a block-type pilot design to lower the mistake rate in downlink radio networks. Regarding Mean Square Error (MSE) evaluation, The Rayleigh frequency selective fading channel was used by the authors to test their suggested channel estimate methodology.
For 2x2 and 2x4 antenna systems, Rima Raissawinda et al. (2014) [4] introduced the MSE channel estimation technique. In order to estimate the channel in a wireless communication method, the authors obtained the channel impulse response. The performance of the channel in terms of MSE and SNR was also examined by the authors. Two highly well-liked algorithms are Expectation Maximization (EM) and Maximum Likelihood (ML) estimation (Ye et al., 2002). [5] Both approaches have their advantages and disadvantages. The benefits of ML outweigh the costs of computational complexity. Although the EM algorithm uses lower order computation, the complexity of its calculations exponentially grows with the amount of transmitted signals (subcarrier). Additionally, it is clear that EM algorithms are typically inappropriate for time-varying channels.
In the presence of interference, channel estimators based on Gaussian noise perform poorly in terms of estimation. Linglong Dai et al. (2013) [6] to avoid poor estimate performance, a Non-Parametric Maximum Likelihood (NPML) evaluate and detect for OFDM systems in the presence of interference were created [7].
The recommended interference detection construction is shown in Figure 1. It efficiently detects and removes the interference between received signals with low power consumption and current consumption with minimum hardware requirements [8].
The main module in OFDM encoder is data level bit converter which is used to convert 7 bit user data into 8 bit discrete sequence. This data level bit converter has XOR modules.
The 7 bit user data are inverted and applied to the XOR gate. The XOR matrix produces 8 bit sequence using the following expressions as,
b1 = h1;
b2 = h1^h2;
b3 = h1^h2^h3;
b4 = h1^h2^h3^h4;
b5 = h1^h2^h3^h4^h5;
b6 = h1^h2^h3^h4^h5^h6;
b7 = h1^h2^h3^h4^h5^h6^h7;
b8 = h1^h2^h3^h4^ h5^h6^h7^h8;
Each orthogonal multiplexer receives two bits from data level bit converter and produces 4 bit pattern, which is the input of 4x1 multiplexer. The multiplexer produces output pattern based on the select lines. The output of the multiplexer will be binary pattern.
The number of one’s is counted and it is compared with number of zeros in this binary pattern. [9] If the number of one’s is greater than or equals to zeros in binary pattern, there is no interference between receiver signals, else there is the formation of interference in received signals. If there is any interference in received signal, the signal is again sent back to decoder circuit to produce the interference free signals.
The MIMO-OFDM transceiver system in this study is created using VHDL codes. Each block and each of its child blocks are individually tested, and any faults are then fixed. [10] For the Multiple Input Multiple Output- Orthogonal Frequency Division Multiplexing (MIMO - OFDM) method and the channel evaluate with interference detection architectural block, test-bench waveforms are produced. Before the design is implemented on an FPGA Fig. 2, the results are compared to those that have already been calculated.
[11] The suggested method conserves more hardware resources and reduces the worst-case disturbance's impact on the channel's estimation inaccuracy under uncertain conditions. Figure 3 The performance-complexity trade-off for this channel estimator with interference detection architecture is favorable [12].
| Algorithm: Channel Estimator with interference detection architecture |
|---|
| Inputs: 7 bit user data from FFT output Output: 4 bit Encoding Sequence for Detector |
| Start Step 1: Obtain transformed data bits from Fast Fourier Transform (FFT) block Step 2: Apply transformed data bits into heuristic converter Step 3: This heuristic converter has XOR matrix produces 8 bit sequence Step 4: Orthogonal multiplexer receives two bits from heuristic converter and produces 4 bit patterns Step 5: Output of the Orthogonal MUX given to input of 4x1 multiplexer Step 6: Multiplexer produces output pattern based on the select lines and output will be binary pattern Step 7: XOR gate receives two bits from heuristic converter and produce one bit into the Parity sequence generator for Error correction Step 8: XOR gate Module produces 4 bit Encoding Sequence from the input of MUX and Parity generator Step 9: Finally Generate 4 bit Encoding Sequence from interference detection architecture for Detector process Step 10: Simulate the recommended architecture with Modelsim 5.5e tool Step 11: Authenticate the simulation outputs Step 12: Xilinx 12.1i software are utilized as synthesis to attain the hardware utilization, current and power dissipations Step 13: Analysis the various parameter like power, current, area and delay Step 14: Implementation of current and power dissipations on various Virtex device Step 15: Validate the results End |
Algorithm
Channel Estimator with interference detection architecture
Inputs
7 bit user data from FFT output
Heuristic converter
Heuristic converter module hasXOR matrix produces 8 bit sequence
b1 = h1;
b2 = h1 xorh2;
b3 = h1 xor h2 xor h3;
.
.
.
b8 = h1 xorh2 xorh3. .. . xorh8;
4.1 Orthogonal multiplexer
Heuristic converter outputs two bits to an orthogonal multiplexer, which outputs four bit patterns. It has two selection lines (S1 and S0), four data inputs (I3, I2, I1, and I0), and one output (Y). The following Fig. 4 displays the 4x1 Multiplexer block diagram.
4.2 Parity Code
XOR gate receives two bits from heuristic converter and produce one bit into the Parity sequence generator Fig. 5
4.3 XOR Module
XOR gate Module produces 4 bit Encoding Sequence from the input of MUX and Parity generator, Finally Generate 4 bit Encoding Sequence from interference detection architecture for Detector process Fig. 6.
This research proposed a MIMO-OFDM channel estimator circuit with interference detection architecture. Using the Verilog Hardware Description Language, the proposed channel estimator circuit with interference detection architecture is created (HDL). In order to assessment the circuit logic of the suggested design, Modata level Bitdelsim 5.5e simulator is utilised. Xilinx Project Navigator 12.1i is then utilized as synthesis software to determine the hardware usage, current and power dissipation.
The Field Programmable Gate Array (FPGA), Virtex devices, and CPLD processors are some examples of the VLSI hardware circuits used to evaluate the proposed channel evaluate with interference finding architecture. Table 1 Demonstrations the Assumption parameters for the simulation execution.
| Parameters | Allotted values |
|---|---|
| Number of symbols | 200 |
| Method of Modulation set-up | 64 - QAM (Quadrature Amplitude Multiplexing) |
| Number of pilot bits | 4 |
| Channel categories | Rayleigh, AWGN and Rician |
| Fast Fourier Transform and Inverse FFT size | 2048 |
In the Table 1, the type of modulation chosen for execution, number of pilot carrier bits needed, different channel environments taken for the evaluation and algorithm used to compute are mentioned in detail.
The suggested channel estimates with interference finding architecture's power and current consumptions on several Virtex family devices are shown in Table 2. The units of power and current usage are milliwatts and milliamps, respectively.
| Family | Device Specifications | Power Dissipation (mW) | Current Dissipation (mA) | Area (nm) | Elapsed time (ns) |
|---|---|---|---|---|---|
| Virtex-E | XCV600E | 236 | 128 | 39 | 64.3 |
| Virtex5 | XC5VLX50T | 34 | 275 | 36 | 56.1 |
| Virtex | XCV200 | 23 | 8 | 27 | 44.9 |
| Virtex-2p | XC2VP2 | 39 | 23 | 26 | 34.9 |
On a Virtex 5 device, the suggested channel estimates with interference detection architecture consumes 310 mW of power, and 20 mW of power is utilized for low power. The recommended channel estimates with interference detection architecture uses a Virtex 5 device and a Virtex device with low power consumption of 270 mA and 8 mA, respectively Fig. 7.
| Family | Device Specifications | Channel Estimator architecture | Channel Estimator with interference detection architecture | ||
|---|---|---|---|---|---|
| Power Consumption (mW) | Current Dissipation (mA) | Power Dissipation (mW) | Current Dissipation (mA) | ||
| Virtex-E | XCV600E | 296 | 164 | 228 | 128 |
| Virtex5 | XC5VLX50T | 398 | 303 | 314 | 274 |
| Virtex | XCV200 | 31 | 12 | 23 | 8 |
| Virtex-2p | XC2VP2 | 47 | 28 | 39 | 22 |
Table 3 demonstrations the analysis of current and power dissipations on Virtex Processors of channel estimator with and without interference detection architecture.
From Table 3, it is very clear that the recommended channel estimates with interference detection architecture dissipates less power and current consumption on Virtex processors. The proposed system consumes 296 mW and 228 mW of power consumptions for channel estimator with and without interference detection architecture on Virtex-E processor, respectively.
For the channel estimator with and without interference detection architecture on the Virtex-5 processor, the proposed system consumes 398 mW and 314 mW of power, respectively. For the channel estimator with and without interference detection architecture on the Virtex processor, the proposed system consumes 31 mW and 23 mW of power, respectively. For the channel estimator with and without interference detection architecture on the Virtex-2p processor, the proposed system consumes 47 mW and 39 mW of power, respectively.
Figure 8. The proposed system consumes 164 mA and 128 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-E processor, respectively. The proposed system consumes 303 mA and 274 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-5 processor, respectively.
Figure 9. The proposed system consumes 13 mA and 8 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex processor, respectively. The proposed system consumes 28 mA and 22 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-2P processor, respectively.
Table 4 shows the performance analysis of hardware utilization of proposed methods in terms of slices, Look Up Tables (LUTs), gate counts and IOBs for channel estimator with and without interference detection architecture.
| Hardware utilizations | Channel Estimator architecture | Channel Estimator with interference detection architecture |
|---|---|---|
| Slices | 760 | 706 |
| LUTs | 152 | 128 |
| Gate Counts | 18,716 | 15,852 |
| IOBs | 172 | 152 |
The proposed channel estimator architecture without interference detection consumes 760 numbers of slices, 152 numbers of LUTs, 18,716 numbers of gates and 172 numbers of IOBs on vertex processor.
The proposed channel estimator architecture with interference detection consumes 706 numbers of slices, 128 numbers of LUTs, 15,852 numbers of gates and 152 numbers of IOBs on vertex processor. From Table 5, it is very clear that the proposed MIMO system with inbuilt channel estimation and interference detection architecture consumes less hardware utilization when compared with MIMO system incorporated with channel estimation only, on vertex processor.
Table 5 shows the performance analysis of hardware utilization of proposed MIMO system for Channel Estimator with interference detection architecture on vertex processors.
| Family | Device Specifications | Slices | LUTs | Gate Counts | IOBs |
|---|---|---|---|---|---|
| Virtex-E | XCV600E | 706 | 128 | 15,854 | 148 |
| Virtex5 | XC5VLX50T | 810 | 172 | 18,955 | 170 |
| Virtex | XCV200 | 372 | 75 | 11,062 | 83 |
| Virtex-2p | XC2VP2 | 412 | 87 | 12,813 | 96 |
The Virtex E processor consumes 706 numbers of slices,
128 numbers of LUTs, 15,854 number of gates and 148 numbers of IOBs. The Virtex 5 processor consumes 810 numbers of slices, 172 numbers of LUTs, 18,955number of gates and 170 numbers of IOBs.
| Methodology | Power Dissipation (mW) | Latency (ns) |
|---|---|---|
| Proposed methodology (Channel estimator with interference detection architecture) | 19 | 9.3 |
| Yuehai Zhou et al. (2018) | 26.67 | 14.28 |
| Himanshi Jain & Vikas Nandal (2016) | 28.57 | 17.32 |
| Mennael Shorbagy et al. (2016) | 32.79 | 19.25 |
| DarshanBharwadet al. (2015) | 36.9 | 25.1 |
| Rima Raissawindaet al. (2014) | 45.1 | 32.9 |
| Hardeep Singh et al. (2014) | 49.9 | 39.7 |
The Virtex processor consumes 372 numbers of slices, 75 numbers of LUTs, 11,062 number of gates and 83 numbers of IOBs. The Virtex-2p processor consumes 412 numbers of slices, 87 numbers of LUTs, 12,813 number of gates and 96 numbers of IOBs. Table 6 is the performance comparison–Power dissipation and Latency for Virtex Family devices.
The suggested low power channel estimator architecture with interference finding is compared in Table 7 in terms of power usage and delay on Complex Programmable Logic Devices (CPLD). On CPLD devices, comparisons between the recommended channel estimator and other traditional channel estimators are tested.
| Methodology | Power Dissipation (mW) | Latency (ns) |
|---|---|---|
| Proposed Methodology (Channel estimator with interference detection architecture) | 21.97 | 10.32 |
| Yuehai Zhou et al. (2018) | 31.45 | 18.92 |
| Himanshi Jain & Vikas Nandal (2016) | 48.23 | 21.34 |
| Mennael Shorbagy et al. (2016) | 53.25 | 24.42 |
| DarshanBharwadet al. (2015) | 64.98 | 41.32 |
| Rima Raissawindaet al. (2014) | 70.96 | 57.39 |
| Hardeep Singh et al. (2014) | 51.96 | 30.65 |
The recommended channel estimator with interference detection architecture consumes 10.32 ns of latency while other conventional approaches as Yuehai Zhou et al. (2018) consumed 18.92 ns of latency, Himanshi Jain & Vikas Nandal (2016) consumed 21.34 ns of latency, Mennael Shorbagy et al. (2016) spent 24.42 ns of latency, DarshanBharwadet al. (2015) consumed 41.32 ns of latency, Rima Raissawindaet al. (2014) consumed 57.39 ns of latency and Hardeep Singh et al. (2014) spent 30.65 ns of latency.
Table 8 shows the performance comparison–MSE and BER (Spartan Family devices) of the proposed and conventional systems.
| Methodology | MSE | BER |
|---|---|---|
| Proposed method | 0.0129 | 10− 0.6 |
| Yuehai Zhou et al. (2018) | 0.0312 | 10− 0.4 |
| Himanshi Jain & Vikas Nandal (2016) | 0.0478 | 10− 0.4 |
| Mennael Shorbagy et al. (2016) | 0.0342 | 10− 0.4 |
| DarshanBharwadet al. (2015) | 0.0537 | 10− 0.3 |
| Rima Raissawindaet al. (2014) | 0.0299 | 10− 0.3 |
| Hardeep Singh et al. (2014) | 0.4831 | 10− 0.2 |
This paper proposes an efficient channel estimator with interference detection architecture for MIMO-OFDM system. The proposed interference detection architecture efficiently detects and removes the interference between received signals with low power consumption and current consumption with minimum hardware requirements. The suggested channel estimator with interference finding architecture uses 21 mW of low power on a Virtex 5 device and 312 mW of low power on a Virtex device. The suggested channel estimator with interference finding architecture uses a Virtex 5 device and a Virtex device with low power consumption of 272 mA and 7 mA, respectively.
Ethics Approval and Consent to Participate:
No participation of humans takes place in this implementation process
Human and Animal Rights:
No violation of Human and Animal Rights is involved.
Funding:
No funding is involved in this work.
data availability statement:
Data sharing not applicable to this article as no datasets were generated or analyzed during the current study
Conflict of Interest:
Conflict of Interest is not applicable in this work.
Authorship contributions:
There is no authorship contribution
Acknowledgement:
There is no acknowledgement involved in this work.
- X. Wang, “Sparsity Adaptive-based Stagewise Orthogonal Matching Pursuit Algorithm for Image Reconstruction,” Journal of Engineering Science and Technology Review, vol. 11, no. 2, pp. 19 – 25, 2018. (doi:10.25103/jestr.112.04)
- H.Y. Liu, and C.Y. Lee, “A Low-Complexity Synchronizer for OFDM-Based UWB System,” IEEE Tran. On Circuits and Systems-II: Express Briefs, vol. 53, no. 11, pp. 1296-1273, 2006. (doi: 10.1109/TCSII.2006.882804)
- W. Zhang, F. Gao, H. Minn, and H.M. Wang, “Scattered Pilots-Based Frequency Synchronization for Multiuser OFDM Systems With Large Number of Receive Antennas,” in IEEE Transactions on Communications, vol. 65, no. 4, pp. 1733-1745, 2017. (doi: 10.1109/TCOMM.2017.2652472)
- Y.G. Li, J.H. Winters, and N.R. Sollenberger, “MIMO-OFDM for Wireless Communications: Signal Detection with Enhanced Channel Estimation,” IEEE Transactions on Communications, vol. 50, no. 9, pp. 1471-1477, 2002. (doi: 10.1109/TCOMM.2002.802566)
- L. Dai, Z. Wang and Z. Yang, “Spectrally efficient time-frequency training OFDM for MIMO large scale MIMO system,” Journal of selected areas in communication, vol. 31, no. 3, pp. 251-263, 2013. (doi: 10.1109/JSAC.2013.130213)
- S. Wu, C.X. Wang, H. Haas, M.M. Alwaleel, and B. Ai. “A non-stationary wideband channel model for Massive MIMO communication system,” IEEE transactions on wireless communications, vol. 14, no. 3, pp. 1434-1446, 2015. (doi: 10.1109/TWC.2014.2366153)
- C. Chen, W. Zhong, H. Yang, and P. Du, “On the Performance of MIMO-NOMA-Based Visible Light Communication Systems,” in IEEE Photonics Technology Letters, vol. 30 no. 4, pp. 307-310, 2017. (doi: 10.1109/LPT.2017.2785964)
- A.K. Shrives, “A comparative analysis of LS and MMSE Channel estimation techniques for MIMO-OFDM system,” Journal of innovative research in science and technology, vol. 1, no. 8, pp. 162-167, 2015. (doi:10.1109/HORA55278.2022.9799887)
- Y. Zhou, F. Tong, A. Song, and R. Diamant, “Exploiting Spatial–Temporal Joint Sparsity for Underwater Acoustic Multiple-Input–Multiple-Output Communications,” IEEE Journal of Oceanic Engineering, vol. 46, no. 1, pp. 352-369, 2021.(doi: 10.1109/JOE.2019.2958003)
- S. Pawanr, G.K. Garg, and S. Routroy, “Development of an empirical model for variable power consumption machining processes: a case of end facing,” Arabian Journal for Science and Engineering, vol. 47, no. 7, pp. 8273-8284, 2022. (doi:10.1177/2041297511398541)
- B. Kahouli, B.B. Alrasheedy, N. Chaaben, and R. Triki, “Understanding the relationship between electric power consumption, technological transfer, financial development and environmental quality,” Environmental Science and Pollution Research, vol. 29, no. 12, pp. 17331-17345, 2022. (doi:10.21203/rs.3.rs-591084/v1)
- H.A. Alobaidy, M.J. Singh, R. Nordin, N.F. Abdullah, C.G. Wei et al., “Real-world evaluation of power consumption and performance of NB-IoT in Malaysia,” IEEE Internet of Things Journal, vol. 9, no. 13, pp. 11614-11632, 2021. (doi: 10.1109/JIOT.2021.3131160)