This work proposes a CMOS two-stage ultra-low noise front-end neural amplifier (FENA) that is realized in the UMC 65nm Process. The proposed FENA consists of an operational transconductance amplifier along with incorporated low pass filter (LPF) technique. Due to this technique, FENA circuit provided best performances such as ultra-low input referred noise, ultra-high input impedance and high gain. An algorithm and mathematical noise model are employed to optimize the dimensions of LPF technique and transistor fingers which yield noise-free biasing current and ultra-low input referred noise of 18fv/√Hz at 10 KHz. The ultra-low input referred noise of FENA is achieved by reducing the gate distributed resistance method which is ignored in conventional FEA design. The FENA achieves an ultra-high input impedance of 0.2 TW, while a splendid post-layout gain of 80 dB has succeeded. FENA has layout area of 0.0023 mm2 which consumes lower power consumption of 1 mW under supply voltage of 1.2V. The FENA is found to be less prone to PVT variations as 1mHz of high-pass corner frequency is achieved for robust design. The best performance parameters of FENA could be beneficial for the purpose of deep exploration neural activities in wireless neural monitoring systems.