This research proposed a MIMO-OFDM channel estimator circuit with interference detection architecture. Using the Verilog Hardware Description Language, the proposed channel estimator circuit with interference detection architecture is created (HDL). In order to assessment the circuit logic of the suggested design, Modata level Bitdelsim 5.5e simulator is utilised. Xilinx Project Navigator 12.1i is then utilized as synthesis software to determine the hardware usage, current and power dissipation.
The Field Programmable Gate Array (FPGA), Virtex devices, and CPLD processors are some examples of the VLSI hardware circuits used to evaluate the proposed channel evaluate with interference finding architecture. Table 1 Demonstrations the Assumption parameters for the simulation execution.
Table 1
Simulation setup for Assumption parameters
Parameters | Allotted values |
Number of symbols | 200 |
Method of Modulation set-up | 64 - QAM (Quadrature Amplitude Multiplexing) |
Number of pilot bits | 4 |
Channel categories | Rayleigh, AWGN and Rician |
Fast Fourier Transform and Inverse FFT size | 2048 |
In the Table 1, the type of modulation chosen for execution, number of pilot carrier bits needed, different channel environments taken for the evaluation and algorithm used to compute are mentioned in detail.
The suggested channel estimates with interference finding architecture's power and current consumptions on several Virtex family devices are shown in Table 2. The units of power and current usage are milliwatts and milliamps, respectively.
Table 2
Analysis of the current and power dissipation of Virtex Processors (45 nm size)
Family | Device Specifications | Power Dissipation (mW) | Current Dissipation (mA) | Area (nm) | Elapsed time (ns) |
Virtex-E | XCV600E | 236 | 128 | 39 | 64.3 |
Virtex5 | XC5VLX50T | 34 | 275 | 36 | 56.1 |
Virtex | XCV200 | 23 | 8 | 27 | 44.9 |
Virtex-2p | XC2VP2 | 39 | 23 | 26 | 34.9 |
On a Virtex 5 device, the suggested channel estimates with interference detection architecture consumes 310 mW of power, and 20 mW of power is utilized for low power. The recommended channel estimates with interference detection architecture uses a Virtex 5 device and a Virtex device with low power consumption of 270 mA and 8 mA, respectively.
Table 3
Analysis of the current and power dissipation of Virtex Processors of channel estimator with and without interference detection architecture
Family | Device Specifications | Channel Estimator architecture | Channel Estimator with interference detection architecture |
Power Consumption (mW) | Current Dissipation (mA) | Power Dissipation (mW) | Current Dissipation (mA) |
Virtex-E | XCV600E | 296 | 164 | 228 | 128 |
Virtex5 | XC5VLX50T | 398 | 303 | 314 | 274 |
Virtex | XCV200 | 31 | 12 | 23 | 8 |
Virtex-2p | XC2VP2 | 47 | 28 | 39 | 22 |
Table 3: demonstrations the analysis of current and power dissipations on Virtex Processors of channel estimator with and without interference detection architecture.
From Table 3, it is very clear that the recommended channel estimates with interference detection architecture dissipates less power and current consumption on Virtex processors. The proposed system consumes 296 mW and 228 mW of power consumptions for channel estimator with and without interference detection architecture on Virtex-E processor, respectively.
For the channel estimator with and without interference detection architecture on the Virtex-5 processor, the proposed system consumes 398 mW and 314 mW of power, respectively. For the channel estimator with and without interference detection architecture on the Virtex processor, the proposed system consumes 31 mW and 23 mW of power, respectively. For the channel estimator with and without interference detection architecture on the Virtex-2p processor, the proposed system consumes 47 mW and 39 mW of power, respectively.
The proposed system consumes 164 mA and 128 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-E processor, respectively. The proposed system consumes 303 mA and 274 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-5 processor, respectively.
The proposed system consumes 13 mA and 8 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex processor, respectively. The proposed system consumes 28 mA and 22 mA of current consumptions for channel estimator with and without interference detection architecture on Virtex-2P processor, respectively.
Table 4 shows the performance analysis of hardware utilization of proposed methods in terms of slices, Look Up Tables (LUTs), gate counts and IOBs for channel estimator with and without interference detection architecture.
Table 4
Performance analysis of hardware utilization of proposed methods on vertex-E processor
Hardware utilizations | Channel Estimator architecture | Channel Estimator with interference detection architecture |
Slices | 760 | 706 |
LUTs | 152 | 128 |
Gate Counts | 18,716 | 15,852 |
IOBs | 172 | 152 |
The proposed channel estimator architecture without interference detection consumes 760 numbers of slices, 152 numbers of LUTs, 18,716 numbers of gates and 172 numbers of IOBs on vertex processor.
The proposed channel estimator architecture with interference detection consumes 706 numbers of slices, 128 numbers of LUTs, 15,852 numbers of gates and 152 numbers of IOBs on vertex processor. From Table 5, it is very clear that the proposed MIMO system with inbuilt channel estimation and interference detection architecture consumes less hardware utilization when compared with MIMO system incorporated with channel estimation only, on vertex processor.
Table 5 shows the performance analysis of hardware utilization of proposed MIMO system for Channel Estimator with interference detection architecture on vertex processors.
Table 5
Performance analysis of hardware utilization of proposed MIMO system for Channel Estimator with
interference detection architecture on vertex processors
Family | Device Specifications | Slices | LUTs | Gate Counts | IOBs |
Virtex-E | XCV600E | 706 | 128 | 15,854 | 148 |
Virtex5 | XC5VLX50T | 810 | 172 | 18,955 | 170 |
Virtex | XCV200 | 372 | 75 | 11,062 | 83 |
Virtex-2p | XC2VP2 | 412 | 87 | 12,813 | 96 |
The Virtex E processor consumes 706 numbers of slices, 128 numbers of LUTs, 15,854 number of gates and 148 numbers of IOBs. The Virtex 5 processor consumes 810 numbers of slices, 172 numbers of LUTs, 18,955number of gates and 170 numbers of IOBs.
Table 6
Performance comparison–Power dissipation and Latency for Virtex Family devices
Methodology | Power Dissipation (mW) | Latency (ns) |
Proposed methodology (Channel estimator with interference detection architecture) | 19 | 9.3 |
Yuehai Zhou et al. (2018) | 26.67 | 14.28 |
Himanshi Jain & Vikas Nandal (2016) | 28.57 | 17.32 |
Mennael Shorbagy et al. (2016) | 32.79 | 19.25 |
DarshanBharwadet al. (2015) | 36.9 | 25.1 |
Rima Raissawindaet al. (2014) | 45.1 | 32.9 |
Hardeep Singh et al. (2014) | 49.9 | 39.7 |
The Virtex processor consumes 372 numbers of slices, 75 numbers of LUTs, 11,062 number of gates and 83 numbers of IOBs. The Virtex-2p processor consumes 412 numbers of slices, 87 numbers of LUTs, 12,813 number of gates and 96 numbers of IOBs. Table 6 is the performance comparison–Power dissipation and Latency for Virtex Family devices.
The suggested low power channel estimator architecture with interference finding is compared in Table 7 in terms of power usage and delay on Complex Programmable Logic Devices (CPLD). On CPLD devices, comparisons between the recommended channel estimator and other traditional channel estimators are tested.
Table 7
Performance comparison–Power consumption and Latency (CPLD Family devices)
Methodology | Power Dissipation (mW) | Latency (ns) |
Proposed Methodology (Channel estimator with interference detection architecture) | 21.97 | 10.32 |
Yuehai Zhou et al. (2018) | 31.45 | 18.92 |
Himanshi Jain & Vikas Nandal (2016) | 48.23 | 21.34 |
Mennael Shorbagy et al. (2016) | 53.25 | 24.42 |
DarshanBharwadet al. (2015) | 64.98 | 41.32 |
Rima Raissawindaet al. (2014) | 70.96 | 57.39 |
Hardeep Singh et al. (2014) | 51.96 | 30.65 |
The recommended channel estimator with interference detection architecture consumes 10.32 ns of latency while other conventional approaches as Yuehai Zhou et al. (2018) consumed 18.92 ns of latency, Himanshi Jain & Vikas Nandal (2016) consumed 21.34 ns of latency, Mennael Shorbagy et al. (2016) spent 24.42 ns of latency, DarshanBharwadet al. (2015) consumed 41.32 ns of latency, Rima Raissawindaet al. (2014) consumed 57.39 ns of latency and Hardeep Singh et al. (2014) spent 30.65 ns of latency.
Table 8 shows the performance comparison–MSE and BER (Spartan Family devices) of the proposed and conventional systems.
Table 8
Performance comparison–MSE and BER (Spartan Family devices)
Methodology | MSE | BER |
Proposed method | 0.0129 | 10− 0.6 |
Yuehai Zhou et al. (2018) | 0.0312 | 10− 0.4 |
Himanshi Jain & Vikas Nandal (2016) | 0.0478 | 10− 0.4 |
Mennael Shorbagy et al. (2016) | 0.0342 | 10− 0.4 |
DarshanBharwadet al. (2015) | 0.0537 | 10− 0.3 |
Rima Raissawindaet al. (2014) | 0.0299 | 10− 0.3 |
Hardeep Singh et al. (2014) | 0.4831 | 10− 0.2 |