CT ΣΔ ADCs are known for their high energy efficiency for a given dynamic range, and are widely used due to their inherent anti-aliasing ability, ease to drive features, and relatively loose integrator design. In the CT ΣΔ ADC, the integrator is a particularly critical part, and its gain directly determines the accuracy of ADC. Traditional operational amplifier structures include folded cascode amplifier proposed in literature [1], which adopts three-stage structure to achieve a DC gain of more than 80 dB. It also has high-gain common-mode feedback circuit, which effectively inhibits noise and reduces input mismatch. The amplifier proposed in reference [2] uses the auxiliary amplifier structure to achieve a low frequency gain of 70 dB, which meets the DC gain requirements of the operational amplifier and contributes to the signal-to-noise ratio of the modulator. The input tube uses a very large area to achieve low flicker noise and reduce the sensitivity to mismatch. However, due to the decreasing of supply voltage, the use of traditional gain boosting techniques such as cascode used in [1][2] are limited, it is necessary to achieve high gain of the modulator by means of multiple cascades.
The noise of operational amplifier is the main source of modulator noise. For Σ∆ ADC, the noise directly affects the SNR and the effective number of bits. Literature [3] proposes a current-reused, class-AB, feed-forward compensated operational amplifier, which adds a \({g}_{m}\) booster stage to the feed-forward path to improve the gain. At a large load of 10 pF, the gain of 40 dB and the phase margin of 60 ° can still be maintained within 100 MHz, but the input equivalent noise of 17 \({\mu }\text{V}/\sqrt{\text{H}\text{z}}\) significantly reduces the signal-to-noise ratio. Literature [4] uses the method of chopping Negative-R to suppress in-band noise and increase the signal-to-noise distortion ratio of operational amplifier by 10 dB. However, chopping is only applicable to low frequency, and the fast charging and discharging of capacitors will irreversibly affect the working state stability of CT Σ∆ ADC at the sampling rate of multi-GHz [5]. Therefore, it is necessary to reduce the low-frequency noise by reducing the gain of the low-frequency signal through band-pass filtering, and use a common-mode feedback circuit to stabilize its DC operating point.
The phase margin of the operational amplifier is directly related to the stability of the modulator and can be used to predict the overshoot of the step response of the system. The three-stage operational amplifier in literature [6] uses multipath feed-forward-reverse nested Miller compensation technology to achieve a 2 GHz unity gain bandwidth and a phase margin of more than 60 °. The source degenerate resistor used in the first stage has good noise suppression effect. The operational amplifier in literature [7] uses Gain-boosting technology, which can achieve a 90 dB DC gain and 88 ° phase margin, and is suitable for various low-frequency ADCs due to its excellent performance. However, Due to the failure of traditional compensation methods such as Miller compensation under high frequency conditions, it is necessary to add zeros and adjust the position of poles by feed-forward paths. Besides, to ensure its high frequency stability, a simple operational amplifier topology with fewer internal nodes needs to be selected [8].
Feed-forward operational amplifier is widely used in continuous time Σ∆ ADC due to its few internal nodes and adjustable poles and zeros position. Recent works of feed-forward operational amplifiers include the work in [9] which implements a fourth-order feed-forward operational amplifier of 35 dB gain in 1 GHz, but it has large low-frequency noise and the phase margin can only be kept above 30 degrees. In the case of reference [10], a gain of 43 dB was achieved using a fifth-order operational amplifier at 450 MHz bandwidth. Nonetheless, its input and output stages use supply voltages of 1.8 V and 1 V respectively. It also has a consumption of 101 mW. In [11], a four-stage amplifier is used to achieve a DC gain of 80 dB at a supply voltage of 1.25 V. However, it cannot achieve large gain at high frequency, and the unit gain frequency is only 3 GHz. Reference [12] demonstrates a fifth-order feed-forward compensated operational amplifier which meets the requirements of the modulator at the cost of very large area and power consumption.
In this work, the gain and the positions of zeros and poles of a fourth-order feed-forward operational amplifier are analyzed. The gain and phase margin are improved by adjusting the position of zeros and poles by feed-forward method. The noise is suppressed by adjusting the transfer function and the power consumption is reduced by current multiplexing. In Section 2, the system-level architecture of the feed-forward amplifier is discussed and the design and function of each circuit module are introduced in detail. The main simulation results are presented and tabulated in Section 3. The conclusion is drawn in Section 4.