A High Schottky Barrier iTFET with Control Gate for Low Power Application

doi:10.21203/rs.3.rs-2975360/v1

This research presents a simulated device structure for an Inductive Line Tunneling Tunnel Field-Effect Transistor (iTFET) with a high Schottky barrier and a control gate. We based our design process on real-world production components, factored in actual processing steps, and verified all software parameters to ensure the study's close alignment with practical manufacturing scenarios. Our configuration employs Silicon Germanium (SiGe), a narrow-bandgap semiconductor known for its cost-effectiveness, mature technology, and ability to enhance electron tunneling. We implemented Schottky Barrier Height (SBH) modulation engineering to increase the ON- state current (I_ON) by integrating an electrode into the semiconductor via Schottky contact. To further optimize the device performance, a control gate was included between the source and drain regions. This modification increased the ION and reduced the OFF-state current (I_OFF) through the manipulation of the electric field. The simulation results demonstrated an average subthreshold swing (SS_AVG) of 31.5 mV/dec, an I_ON of 4.96x10^-6 A/μm, and an I_ON/I_OFF ratio of 1.1x10⁸ at a V_DS of 0.2V, indicating a remarkably low subthreshold swing. These outcomes highlight the feasibility of utilizing a low thermal budget approach to fabricate high-performing TFETs that are well-suited for economical and low-energy applications.

control gate

line tunneling TFET

Schottky barrier high

SiGe

As devices continue to scale down, conventional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) encounter a host of challenges due to their operational mechanics, including undesirable effects such as the short-channel effect (SCE), high leakage current, and the 60 mV/decade room temperature subthreshold swing (SS) limit. These complications heighten the power consumption of both the device and the system [1-4]. To mitigate these issues, the Tunneling Field Effect Transistor (TFET) has emerged as a promising alternative to conventional MOSFETs. TFETs leverage the quantum band-to-band tunneling (BTBT) phenomenon for current conduction, yielding lower SS, decreased OFF-state current (I_OFF), and improved immunity to SCEs. Nonetheless, their shortfall lies in the reduced ON-state current (I_ON). Several strategies have been proposed to enhance I_ON, including high-k dielectrics, narrow bandgap materials, double gates, auxiliary gates, line tunneling, and charge plasma [5-10]. Our work introduces a high Schottky barrier Inductive Tunneling TFET (iTFET) with a control gate that amalgamates all these benefits to improve I_ON.

Our novel iTFET employs a Schottky contact [32] to form drain regions, leveraging a suitable metal work function in the drain area [11,25,30]. Unlike traditional TFETs, which require doping to create p and n regions leading to P-I-N or P-N-N structures [14][15], our proposed iTFET necessitates a one-time doping to convert the structure into a P⁺⁺-type body. As a result of band bending, thermally activated electrics engender an inversion layer, which transmutes the drain region into an N-type [30], resulting in a comprehensive P⁺⁺-N⁺ structure that mitigates the effects of dopant diffusion [12] [13,16-18]. Furthermore, we integrate a control gate between the source and drain to augment device performance [19-21]. This not only boosts the ON-current (I_ON) but also curtails the OFF-state current (I_OFF), resulting in enhanced overall device efficiency. The control gate proves advantageous in situations where there is a manufacturing process gap, as it can suppress point tunneling and reduce leakage current.

SiGe material, as exhibited in prior research, presents superior device performance due to its narrow bandgap, which lessens resistance, and its larger germanium content that expands or contracts the transistor channel, thereby improving mobility. This allows transistors to operate quickly at low voltage while reducing leakage current. The cost of the SiGe process is comparable to the mature and low-cost silicon process, and major companies such as TSMC, Samsung, and Intel have adopted SiGe as a material. Furthermore, the narrow bandgap lends itself to the tunneling mechanism, which benefits high TFET on-current and low onset voltage. Notably, line tunneling has demonstrated superiority over point tunneling [22]. Device structures based on line tunneling achieve steeper average switching characteristics and higher on-currents than their point tunneling counterparts [23][24].

Given these advantages, an iTFET with a control gate is a promising approach for achieving high-performance TFET. In this work, we propose an iTFET with a control gate to enhance the ON-state current (I_ON) and performance, with potential applications in future Internet of Things (IoT), big data, AI, and low-power implementations. The remaining paper is organized as follows: Section II details the device configuration and simulation model. Section III delves into the comparative analysis of the molar fraction, control gate voltage, trap interface effect, and quantum confinement effect, along with the variability analysis of the devices' configuration. Section IV provides a conclusion to the study.

TABLE I This Design Parameter For Simulation iTFET With Control Gate

Parameters	Value
Body thickness (nm), t_Body	5
Body doping - Boron (cm^-3)	1e19
Main gate length (nm), L_MG	100
Source length (nm), L_Source	100
Gap length (nm) L_Gap	5
Control gate length (nm), L_CG	5
Drain length (nm), L_Drain	3
Body material	Si_0.7Ge_0.3
Oxide material	HfO2
Gate work function (eV)	3.7
Gate oxide thickness (nm)	3
Control gate oxide thickness (nm)	3
V_DS (V)	0.2
Source contact	Ohimc
Drain contact	Schottky

Fig. 1(a) depicts the cross-sectional view of the iTFET with a control gate, while Fig. 1(b) shows the iTFET without a control gate. The N⁺ region (drain) is created by a suitable metal work function, which is an essential feature in this concept. First, the work function of the metal should be different from that of the semiconductor. For P-type semiconductors, when the work function Ф_m < Ф_s[40], an N-type region can be formed through the Schottky contact [30]. Therefore, the N⁺ region can be formed by using a metal with a lower work function to create a Schottky contact at the drain [31].

The device simulations are carried out using TCAD Sentaurus [26], which uses nonlocal band-to-band tunneling model to calculate the tunneling generation rate. The Shockley – Read – Hall and Auger recombination models are adopted to include the effect of carrier recombination. Some other models, including interface trap, band gap narrowing, concentration dependent, and field-dependent mobility models, are also considered. As our propose device thickness is 5nm, which quantum mechanical effects have been considered in this paper. For film thicknesses below 10 nm, a quantum confinement model has to be enabled in the simulations [27].

The possible fabrication steps to realize iTFETs are discussed here. Initially, bulk SiGe wafers were used as substrates [Fig. 2(a)] to form fins through a mask using dry etching [43][Fig. 2(b)]. The gate oxide is deposited at a specific angle using 45° magnetron sputtering [42][Fig. 2(c)]. Subsequently, oxide deposition is performed, and chemical mechanical polishing (CMP) is used to remove the top of the HfO2 and SiO2 layers [Fig. 2(d)]. This is followed by the deposition of metals [Fig. 2(e)]. Next, SiO2 is deposited, and another round of CMP is performed to grind off excess oxide and metal from the top surface [45] [Fig. 2(f)]. Selective wet etching is employed to remove a portion of the metal [Fig. 2(g)], and HfO2 is deposited to fill the pores [43] [Fig. 2(h)]. Another round of selective etching is used to remove part of the oxide [Fig. 2(i)], and metal is deposited on top [Fig. 2(j)]. The drain region is formed by using a mask and etching the metal [Fig. 2(k)]. Following that, oxide is deposited [Fig. 2(l)], and a hole is etched by using electron beam[], which is then filled with metal [Fig. 2(m)]. Subsequently, a portion of the metal is removed by selective etching [Fig. 2(n)]. Finally, the contacts for accessing the source, drain, and gate are formed [44] [Fig. 2(o)].

Additionally, Fig. 3 includes an inset showing the calibration result for simulating a DG (Double Gate) Tunnel Field-Effect Transistor (TFET). Through the adjustment of simulation parameters, we were able to achieve a good agreement with the measurements reported in [41], thereby validating the quality and accuracy of our various simulation results.

A. Device Performance Comparison with Difference Control Gate Voltage

In Fig. 4(a) and (b), the electron concentration diagram is displayed when V_MG= 0V, revealing a comparatively dense electron concentration in the drain region, as the semiconductor itself is P-type doped. The use of a suitable metal in the drain region allows the structure to become P⁺⁺-N⁺. The simulation design parameters utilized in this study are presented in Table I. It is important to note that there should be no gap between the source and control gate, nor between the drain and control gate, to achieve low leakage current and high ON-state current (I_ON).

For low-power applications, the device is designed for low voltage with V_DS set to 0.2V, and the control gate voltage is set below 0.6V or above -0.6V. In Figure 5(a)(b), the performance of the device with different control gate voltages is shown, and it is evident that increasing the control gate bias improves the I_ON/I_OFF ratio. The average subthreshold swing (SS_AVG) and minimum subthreshold swing (SS_MIN) are between 25 mV/dec to 32 mV/dec and 7 mV/dec to 15 mV/dec, respectively, when the control gate bias is between – 0.6V and 0.6V. When the control gate bias is at 0.2V, the I_ON is 4.96 × 10^-6 A/μm, and the I_ON/I_OFF ratio is 1.1 × 10⁸ A/μm. The average subthreshold swing (SS_AVG) is 31.5 mV/dec, and the minimum subthreshold swing (SS_MIN) is 12 mV/dec. When comparing the results with and without a control gate structure, we observe that although the average subthreshold swing (SS) of the control gate increases slightly, a higher on-current and lower leakage current can be achieved, resulting in a significant improvement in the I_ON/I_OFF ratio. The most beneficial result is obtained when the control gate voltage bias is 0.2V, which is suitable for low-power applications with a low voltage supply. This results in a 264% increase in I_ON/I_OFF ratio and an 87% increase in I_ON compared to the device without a control gate structure. The average subthreshold swing (SS_AVG) is 31.5 mV/dec and the minimum subthreshold swing (SS_MIN) is 12 mV/dec.

To enhance our comprehension of control gate engineering in iTFET, we showed contour plots depicting the nonlocal e-BTBT rates for three different structures: a V_MG = 0.6 V iTFET without a control gate, an iTFET with V_CG= 0.2V, and an iTFET with V_CG= -0.2V. These plots are presented in Fig. 6(a)-(c). The iTFET with a control gate shows greater I_ONcompared to the iTFET without a control gate due to larger electron band-to-band generation rates in the line tunneling region (source region), as demonstrated in Fig. 6(d). This increase in BTBT rate is primarily attributed to the presence of the control gate, which generates an additional electric field and enables the energy bands to overlap more, as shown in Fig. 6(e).

Fig. 7(a)(b) displays the electric field at V_MG= 0V and V_MG= 0.6V. When comparing the structures with and without a control gate, a significant reduction in the electric field at the drain is observed when a control gate is used, leading to a reduction in I_OFF. In Fig. 7(b), it can be observed that the inclusion of a control gate between the source and drain leads to an increase in the electric field strength in the source area. This elevated electric field strength can enhance the ON-state current (I_ON) by improving the e-BTBT generation rate and facilitating tunneling, as demonstrated in Fig. 6(d).

B. Impact of Mole Fraction and Schottky Barrier High Variations on the Performance of the Electrical Characteristics of iTFET

TABLE II [29] SIGE Parameter In Mole Simulation

Material	Electron Mobility	Band Gap
Si	1400 cm²/Vs	1.12eV
Si_0.9Ge_0.1	964 cm²/Vs	1.074eV
Si_0.8Ge_0.2	533 cm²/Vs	1.028eV
Si_0.7Ge_0.3	101 cm²/Vs	0.982eV
Si_0.6Ge_0.4	330 cm²/Vs	0.936eV
Si_0.5Ge_0.5	761 cm²/Vs	0.89eV

TABLE III SBH Parameter Simulation

SBH (eV)	I_ON/I_OFF ratio (A/μm)	SS_AVG (mV/dec)
0.7	7.3×10⁶	30.9
0.75	2.31×10⁶	28.7
0.8	5.9×10⁷	30.7
0.85	1.1×10⁸	31.5
0.9	1.22×10⁷	39.1
0.95	2.35×10⁶	44.4

Table II presents the electron mobility and band gap of SiGe with mole fraction. It can be observed that the band gap reduces as the germanium content increases. However, the electron mobility shows a non-linear dependence on the germanium content. Specifically, in Si_0.7Ge_0.3, even though the electron mobility is relatively low, it exhibits the highest performance with a higher I_ON/I_OFF ratio and a lower subthreshold swing, as shown in Fig. 8(a)(b). Increasing the germanium content leads to a higher on-state current and a lower band gap, but also results in increased leakage current. However, in this structure, the band gap is the most crucial factor. Thus, despite Si_0.7Ge_0.3 having a lower electron mobility than other compositions, it possesses the most suitable band gap.

Fig. 9 illustrates the variation in drain work function for different values. It is observed that increasing the Schottky barrier height results in higher on-state current. As depicted in Fig. 10(a)(b), higher SBH leads to an increase in carrier concentration at the drain area, resulting in a denser N-type region and higher Ion. However, increasing the Schottky barrier height also leads to higher off-state current (I_OFF). Table III presents the performance of various Schottky contacts on the drain side, with excessively high or low Schottky barrier heights leading to degraded performance

Therefore, the optimal option is a Schottky barrier height of 0.85eV, which has the highest I_ON/I_OFF ratio and better SS_AVG value of 1.1×10⁸ I_ON/I_OFF ratio and 31.5 (mV/dec), respectively.

C. Device Performance Comparison with Negative Effect

As we are aware, the wafer foundry process is not perfect. Fig. 11 illustrates a gap modulation between the source/control gate and control gate/drain. In Fig. 12, it can be observed that increasing either gap1 or gap2 leads to poorer performance, resulting in reduced ON-state current (I_ON) and increased OFF-state current (I_OFF). Fig. 13(a) to (e) shows that point tunneling generates leakage current when the channel is at V_MG= 0V. Notably, when both gap1 and gap2 are at a distance of 3nm, the leakage current generated by point tunneling is most noticeable. Fig. 14(a) to (e) provides an explanation for why point tunneling leads to an increase in leakage current. As the gap increases, the conduction and valence bands overlap, thereby increasing the electron tunneling probability. Table IV shows that increasing the gap length results in a larger channel and longer tunnel distance. Although the conduction and valence bands overlap when the gap exceeds 1nm, the overlap area is not too significant. However, when the gap is at 3nm, the overlap area increases, and tunneling is not too long, which leads to an increase in point tunneling.

To solve the issue of point tunneling, we can modify the control gate voltage. As depicted in Fig. 15(b), the addition of the control gate results in the bending of the energy band. When a positive bias is applied, the energy bands overlap,

TABLE IV Gap Parameter Simulation

Gap1/Gap2 (nm)	Ec/Ev Overlap(eV)	Channel Length (nm)
1/1	0.033557	7
3/3	0.100484	11
5/5	0.102599	15
7/7	0.104656	19

leading to increased leakage current and a rise in OFF-state current (I_OFF), as shown in Fig. 15(a). To eliminate this, we can apply a negative bias to bend the energy band upwards, causing no overlap between the energy bands and reduces leakage current. To ensure accurate analysis, we must take into account the quantum confinement effect, especially.

since the substrate thickness is less than 10nm. In order to incorporate this effect, we used the thin-layer Lombardi model in Sentaurus [26] and observed a minor reduction in the ON-state current (I_ON) from 4.2% to 4.8%, and an increase in SS_AVG from 4.8% to 8.2% in Fig. 16. However, it is important to note that TFET may encounter interface traps, which can negatively impact its OFF-state behavior and cause large deviations from ideal characteristics. Fig. 17 demonstrates that when the trap concentration increases, taking into account donor and acceptor trap charges [28], there is a deterioration in electrical performance, leading to higher leakage currents. Nevertheless, if the concentration remains lower than 1E12 (cm-³), the effect on performance is not significant. In Fig. 18, a benchmark of low-power devices proposed in recent years is presented. Our proposed structure not only achieves good subthreshold swing (SS) without negative -capacitance (NC), SOI or using III-V compound semiconductor, but also exhibits good I_ON/I_OFF performance. Moreover, the structure requires only 0.2V_DS, which reduces the power supply when compared to other components, resulting in significant energy consumption reduction.

In this study, we propose and evaluate a novel tunnel field-effect transistor (TFET) that utilizes a high Schottky contact instead of ion implantation to induce minority carrier holes in the P-type body to invert the N-type region. Additionally, we utilize line tunneling and a control gate to improve TFET characteristics, resulting in an improved I_ON/I_OFF ratio and low power supply application. Furthermore, our fabrication process requires only one-time doping, making it simple and low in thermal budget. Our device achieved an I_ON of 4.96 × 10^-6 A/μm and an I_ON/I_OFF ratio of 1.1 × 10⁸A/μm at V_DS = V_CG = 0.2V, along with SS_MIN of 12 mv/decade and SS_AVG of 31.5 mv/decade. We also discovered that adding a gate between the source and drain respectively dominates the device performance for the negative and positive gate regions. However, if the gap between the source, control gate, and drain is too long, a high leakage current can occur, resulting in worse SS. To resolve this issue, changing the voltage to become negative can reduce the problem of high leakage current. Additionally, we discuss the quantum confinement effects and interface traps that can reduce the ON-state current (I_ON) and increase the leakage current. However, these effects are not significant enough to have a major impact on performance. Our novel iTFET with control gate structure has the potential to meet future low-power applications such as the Internet of Things (IoT), big data, and AI.

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No competing interests reported.

A High Schottky Barrier iTFET with Control Gate for Low Power Application

Status:

Version 1

Abstract

Figures

I. Introduction

II. Simulation Models And Device Structure

Iii. Results and Discussion

Iⅴ. Conclusion

References

Additional Declarations

Status:

Version 1