IoT based Investigation of Augment March C _ Algorithm: Heuristic Approach

doi:10.21203/rs.3.rs-3012516/v1

In this paper an effective novel memory management strategies for IoT framework standard over MQTT with raspberry pi field protocol is used in RAID 6 (Redundant array of independent drives) for data storage. RAID 6 offers a long data retention time for archiving as well as it provides a high fault and drive failure tolerance rate. The probability of rebuild failure rate as proposed to 0.397%with RAID 5. In This paper we have proposed a memory management strategies based on IoT framework for effective testing and repairing. For this a novel memory testing approach i.e. Improvised March C- (IM-March C-) Algorithm has been used with cases 32*8*1, 64*8*1, 256*8*1 for certain predefined injected-random fault at certain location in a RAID 6. The presented work has been tested on SPARTAN 2E, SPARTAN 3E, VIRTEX 2, VIRTEX 4, VIRTEX 5. From the Results it is clear that proposed algorithm has better fault coverage, require less tracing time (0.14 sec) and better device utilization.

IoT Framework

IoT Gateway and Smart Device

Master Accelerator

MBIST

MBISR

RAID 6

In the current scenario multiple sensor are connected to multiple smart devices to acquire data high speed with secure communication .For this an novel IoT (Internet of Thing) technology is used for real time tracking of data. An IoT is a smart network which works on certain protocols for communicating the information with the sensor devices. It identifies, track, locate, monitor and manage the thing in real time environment.

IoT require certain set of rule to process the data for this an IoT protocol are used. There are two type of protocol used IoT network protocol and IoT data protocols [31]. IoT network protocols are set of rule for connecting the many devices on the same network these are LTE, CAT 1, LTE CATM 1, NB-IoT, Bluetooth, Zigbee, Lora wan .IoT data protocol are standards for connecting and exchange data with each other at certain network. Data protocols are AMQP (Advance message Queuing) this is an open messaging standards, MQTT (Message queue telemetry transport) this is the sub messaging protocol used for connecting low power devices where memory requirement is less, HTTP (Hyper text transport protocol) is require for secure data communication for world wide web, CoAP (Constrained Application Protocol) is used for saving the battery life and for increasing the storage capacity while reducing the data requirement to operate, DDS (Data Distribution Service) it is used for real time data distribution, LWM2M (Light weight machine to machine Protocol) is designed for the machine to machine remote management with fast IoT solutions.

In this paper, we have used an MQTT protocol with raspberry pi field protocol memory testing and repair. RAID 6 memory array is used for memory testing. RAID 6 is a redundant array of independent disk. It provide high fault driven and failure tolerance with high data retention time period like archiving. This system is less prone to fault during the disk rebuilding process [20] [21].As the requirement of high speed, lower power and high integration memories is increased for the unknown rate as 5G communication, cloud computing, artificial intelligence[32] and other major contributors of generation. We have used 32*8*1, 64*8*1, 256*8*1 memory array as disk in RAID 6 for testing.

Memory testing algorithms are used to test memory Faults. Faults in memories are generally caused due to open and short circuits in the memory cells, errors in the address decoder [4], and errors in reading and writing logic operations. These faults are classified as stuck at fault (memory cell is stuck at logic one), Stuck open fault (memory cell is stuck at logic zero), Transition fault (once the logic is defined then it is inaccessible back), Neighborhood pattern sensitive faults (memory cell can change its cell value with the influence of the neighborhood cell), Coupling fault [3], [4].What is BIST.

BIST controllers provide fault-free memories. This controller works on memory testing algorithms. The quality of testing algorithms is defined by the fault coverage concerning the FFM (Function Fault Model) [9], [10]. There is the number of March testing algorithms have been designed [11]. They have proposed a March DSS algorithm for simple static faults with certain conditions for fault coverage [12]. They have generated a March LSD algorithm for 75N complexity to detect all linked static and dynamic faults but are not suitable for unlinked faults [13]. They have designed the March LR algorithm to detect realistic linked faults [14]. They have designed the March PS algorithm for complexity of 23 N to detect DRAM pattern-sensitive faults coverage [15]. They have proposed March SS with the test length of 22N which is cable to detect all really simple static faults in RAMs but it can't detect linked faults [16]. They have designed the March NS algorithm to detect neighborhood pattern-sensitive faults with SAF, TF, CF, and AFs. It deals with single-bit errors for 2D memories [17] .In this, they proposed a polynomial algorithm to automatically generate a march test this method reduces the complexity and testing time and can cover static, dynamic, and all linked faults.

This paper is categorized into four sections. Section 1 describes the proposed IoT Framework in edge computing using Gateway and RAID 6. Section 2 covers the effective memory management unit for memory testing and repair. Section 3 presents the comparative result of the proposed algorithm and in Section 4 the conclusion and future scope of the proposed work to been mentioned.

Figure 1 show the proposed IoT framework standard MQTT with raspberry pi field protocol for memory testing and repair. This architecture is sub-divided into three parts: Master Accelerator, Gateways & smart devices [20], and Memory Management Unit (MMU) [21].

1.1 Master Accelerator (MA)

The Master Accelerator (Board Com’s PCI 9000 series) main task is to monitor, collection, analyses and process the information to further stages. It provides information regarding the selection of memory testing algorithms including pattern for March elements. The block also performs the normalization and optimization of the selected algorithm [22][23]. In this paper, we have used the IM-March C- Algorithm. Therefore, this block selects this algorithm in its default settings. At the end, a fault dictionary is prepared which is connected to display (LCD) for real time monitoring on the application container which allows the application to update concurrently. In this paper, a network device (raspberry pi) [24] is used with data management messaging having MQTT (Message Queuing Telemetry Transport) IoT protocols for Real-time monitoring [23][25].

1.3 Memory Management Unit (MMU)

The MMU block Provides assistance to MA block. It consists of sub blocks [MUT array (RAID 6), Memory Testing and Validation, Routers, Fault Classifier, Fault Dictionary, MBISR module. Further classification of this unit is described in section 2.

MMU is used for effective Memory testing and repairing as shown in Figure 2. For memory testing a novel memory testing approach is proposed Improvised March C- (IM March C-) Algorithm. We have used this algorithm over following cases 32*8*1, 64*8*1,256*8*1 for fault detection in a RAID 6. This algorithm is derived from the parent algorithms. These faults are injected randomly without any connection to each other at certain predefined locations.

2.1 RAID 6

We have used three memories cases 32*8*1, 64*8*1 and 256*8*1 array as disk in RAID 6. These memories array are allocated through the memory allocation job manager with run time selection on MUT. RAID 6 is used to increase the performance and reliability of the data storage [20] [21]. It is also known as double parity redundant array of independent drivers. It can continue the operation even if it faces disk failure twice. It provides enhanced fault tolerance capability.

2.2 Memory Testing and Validation

For memory testing and validation, we have proposed an IM-March C- algorithm for fault detection. The proposed algorithm adheres to the feature of its parent algorithm March C-.Difference between March C- and Proposed Improved March C-.

Proposed Algorithm is designed with Complementary pairs of March C- elements.
M2’ and M3’ contains all sensitive operators (rd0, wr1, rd1, wr0) which are cable of detecting all coupling CFs [33].
All linked faults will also detect in the ↑ address order.
An comparison between March C- and proposed is shown in Table 1.
M1’, M2’, M3’will also detect the SAF 0/1, TF, Address decoder fault.
As number of March element are reduced in IM March C- (M4’) by complementary the March C- element (M5’, M2’) and (M4’, M3’).This reduces its testing power as well as its testing time power consumption [34].

Table 1: Faults detected

Algorithm Used	SAF0/1	TF	CFs	AF	Linked Faults
March C-	✓	✓	✓	✓	---
IM March C-	✓	✓	✓	✓	✓

We have injected one Stuck- at-faults at memory location (1, 2) , two transition faults at memory location (0, 0) , (0, 1) ,(2,2) and (2,3) and one coupling faults at memory location (3, 2) and (3, 3) as shown in Figure 3. These faults are randomly selected faults with non-resemblance. Figure 3 shows the 4x4x1 memory size in which faults are injected and memory testing is performed using the proposed Improvised March C- algorithm.

Table 2, shows the proposed IM- March C- algorithm. Algorithm 1 has four March elements. In Step 1, write Zero operation is performed in the first March element in any direction. In step 2 the second March element will read the expected one and write with zero at the last address location with expected read zero and write one in the upwards direction. In Step 3, the third March element read the expected zero and write one at the last address location with read expected one and write zero in a downwards direction. At last in step 4, the March fourth element will read the expected one in any direction. The proposed algorithms are compared with March C- for fault coverage, tracing time and device utilization.

Table 2 IM- March C- algorithms

Algorithm1 IM- March C-

Step1: ↕ wr0

Step2: ↑rd1, wr0, rd0, wr1

Step3: ↓rd0, wr1, rd1, wr0

Step 4:↕ rd1

2.2.1 Methodologies used in the proposed Improvised March C- test algorithm

Figure 4, shows the state diagram of the proposed algorithm which is adhered to on March C-.The notations used in proposed algorithm are as follows

Qn: March Elements

T: Test signal (1= Test Mode and 0=Normal Mode)

CLR: Clear address to the memory location 0

LA: Last address

DO: Data Out

QnB: Beginning of March elements

Qnr: Read data

Qnw: Write data

States/March elements Q0and Q1 detects the stuck-at-1 faults and transition faults.Q1, Q2, and Q3 detect stuck-at-0 faults, transition faults, and coupling faults. This State diagram is working in two-modes. First, Normal mode (at T=0) with the last address which is rolled over to the last memory location (LA=0) this is when memory is in the idle phase. Second, when memory testing start then it is Test mode (at T=1) with last address which is rolled over to the last memory location (LA=1)

The flow chart of the proposed algorithm is shown in Figure 5.Memories under test are initially working at normal mode and once the testing start then it switches to test mode. In test mode four March elements perform the read and write operation based on defined directions (upward/downward/irrelevant). When memory testing is completed an error fee memory is achieved with the Fault dictionary which is generated at every read operation.

2.2.2 Simulation profile of proposed Improvised March C- test algorithm

Figure 6 shows the RTL top view of the MUT for 32x8x1 memory size. In this MUT an address array is 5 bit(0 to 4),data_in and data_out are 8 bit (0 to 7), and fault bit out is 8 bit (0 to 7). A proposed algorithm is applied to MUT whose RTL top view is shown in Figure 7 using Xilinx ISE suite. In this clock, reset, test, last address, and data out are input signals, and count, clear, data in, write_CMD , up address and first address are output signals.

Figure 8 and 9 show the test bench waveform of MUT 32*8*1 and proposed IM March C- algorithms, in this state change in input-output signals are shown as explained in the state diagram.

2.3 Process to Repair the Faulty Memories (MBISR)

In the memory repairing process, MBISR (Memory build- in self Repair) block is used to repair the faults. In this block a solution of Faulty memories are predicted on the basis of selected memory repair algorithm.

In this Section, the tradeoff performance of March C- and Proposed IM March C- is analyzed. As shown in Table 3 testing time required by the proposed algorithm for fault coverage for address length 10N is less as compared to March C-. This simulation profile for fault coverage is conducted on MATLAB. Timing details and device utilization performance of MATS+, March C- and proposed IM is shown in Table 4 and Table 5 implemented using the Xilinx ISE suite.

3.1 Trade-off performance of proposed and March C-

Table 3 shows the trade off performance of March C- with proposed IM- March C- based on tracing time and fault coverage. Address length is defined as 10N. This trade-off performance is also simulated with MATLAB. Figure 10 shows the tracing time comparisons of March C- and IM- March C-Algorithm.

Table 3 Trade-off Performance based on testing time, Fault Detected, and Address length (Complexity)

S.No.	Algorithms	Tracing Time(MATLAB)	Fault Detected	Address length(Complexity)
1	March C-	0.25 Sec	SAF, ADFs, TF, CFs	6*6(10N)
2	Proposed Improvised March C-	0.14 Sec	SAF (2), TF(2), and, CFs (2)	6*6(10N)

3.2 Timing Details

Table 4 shows the minimum input arrival time before the clock and Maximum output required time after the clock for MATS+, March C- and proposed IM-March C-. These testing algorithms are synthesized and implemented on Spartan 2E, Spartan 3E, Virtex 2, Virtex 4, and Virtex 5. Here, the minimum input arrival time of the proposed IM March C- algorithm required comparatively less time than MATS+ and March C-. Figure 11 shows the comparisons of these algorithms over different selected Devices. Here Ta defines the arrival time and Tr defines the required time.

Table 4 Time required for input and output signals

S.No.	Device Selected	MAT+		March C-		Proposed Improvised March C-
S.No.	Device Selected	Minimum i/p arrival time before the clock	Maximum o/p required time after the clock	Minimum i/p arrival time before the clock	Maximum o/p required time after the clock	Minimum i/p arrival time before the clock	Maximum o/p required time after the clock
1	Spartan 2E	3.509 ns	6.613 ns	4.139 ns	6.613 ns	4.139 ns	6.609 ns
2	Spartan 3E	2.6878 ns	7.078 ns	2.894 ns	7.078 ns	2.892ns	7.078 ns
3	Virtex 2	2.011 ns	4.659 ns	2.096 ns	4.659 ns	2.096 ns	4.599ns
4	Virtex 4	1.442 ns	3.879 ns	1.422 ns	3.879 ns	1.422 ns	3.869 ns
5	Virtex 5	1.211 ns	2.699 ns	1.211 ns	2.699 ns	1.211 ns	2.670 ns

3.3 Device Utilization performance

Table 5, shows the device utilization performance for MATS+, March C- and proposed IM March C- based on the number of slices, Number of slice flip flops, Number of 4 input LUTs, Number of bonded IOBs, and number of GCLKs used and their utilization. Implemented on Spartan 2E, Spartan 3E, Virtex 2, Virtex 4, and Virtex 5. Figure 12 shows the Device Utilization Comparisons Performance as mentioned in Table 5.

Table 5 Device Utilization Performance of MAT+, March C- and Proposed Algorithm

S. No.	Device Selected	Parameters	MAT+			March C-			Proposed Improvised March C-
S. No.	Device Selected	Parameters	Used	Available	Utilization	Used	Available	Utilization	Used	Available	Utilization
1.	Spartan 2E	Number of Slices	14	768	1%	25	768	3%	25	768	3%
		Number of Slice Flip Flops	22	1536	1%	42	1536	2%	42	1536	2%
		Number of 4 input LUTs	25	1536	1%	41	1536	2%	39	1536	2%
		Number of bonded IOBs	11	124	8%	11	124	8%	11	124	8%
		Number of GCLKs	1	8	12%	2	8	25%	2	8	25%
2.	Spartan 3E	Number of Slices	14	768	1%	25	768	3%	25	768	3%
		Number of Slice Flip Flops	22	1536	1%	42	1536	2%	42	1536	2%
		Number of 4 input LUTs	25	1536	1%	41	1536	2%	41	1536	2%
		Number of bonded IOBs	11	98	11%	11	178	6%	11	178	6%
		Number of GCLKs	1	4	25%	2	4	50%	2	4	50%
3.	Virtex 2	Number of Slices	14	256	5%	25	256	9%	25	256	9%
		Number of Slice Flip Flops	22	512	4%	42	512	8%	42	512	8%
		Number of 4 input LUTs	25	512	4%	41	512	8%	41	512	8%
		Number of bonded IOBs	11	88	12%	11	88	12%	11	88	12%
		Number of GCLKs	1	16	6%	2	16	12%	2	16	12%
4.	Virtex 4	Number of Slices	14	6144	0%	25	6144	0%	25	6144	0%
		Number of Slice Flip Flops	22	12288	0%	42	12288	0%	42	12288	0%
		Number of 4 input LUTs	25	12288	0%	41	12288	0%	41	12288	0%
		Number of bonded IOBs	11	240	4%	11	240	4%	11	240	4%
		Number of GCLKs	1	32	3%	2	32	6%	2	32	6%
5.	Virtex 5	Number of Slices	22	192000	0%	42	19200	0%	42	19200	0%
		Number of Slice Flip Flops	5	27	18%	7	49	14%	7	49	14%
		Number of 4 input LUTs	7	27	25%	36	19200	0%	36	19200	0%
		Number of bonded IOBs	11	220	5%	11	220	5%	11	220	5%
		Number of GCLKs	1	32	3%	2	32	6%	2	32	6%

There is no difference in March C- and proposed Improvised March C-.On the basis of implementation outcome are mentioned in table 5.However the LUTs and bounded IOBs gives benefits over MAT+. The proposed algorithm adheres to the feature of its parent algorithm March C-.Difference between March C- and Proposed Improved March C- is discussed in section 2.2.As from Table 4 the proposed IM March C- time required for input and output signals arrival time before and after the clock is less as compare to March C-.

With the advancement in IoT and supportive edge computing technology the role of linked memory devices become crucial with time. The memory intensive applications demands the suitable memory management strategies are required for real time and fast switching operation along with fault tolerance. The presented work is focused on such a role of memories used as a disk in RAID 6 in conjunction with IoT framework of edge computing. The presented architecture composed of Master Accelerator(MA),Gateway and smart devices(GSD) and memory management Unit(MMU).As the work is focused on MMU, So cases as disk in RAID 6 were 32x8x1, 64x8x1 and 256x8x1 with injected random faults were taken. The MMU provides testing, repair solutions to the MA with the help of IoT framework. For testing purpose an IM March C- algorithm is been proposed which adhere from its parent algorithm March C-. The result shows the better fault coverage, less tracing time (0.14sec) for IoT framework module. The device utilization tested over Spartan 2E, Spartan 3E, Virtex 2, Virtex 4, and Virtex 5.

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No competing interests reported.

IoT based Investigation of Augment March C _ Algorithm: Heuristic Approach

Status:

Version 1

Abstract

Figures

Introduction

1 Proposed IoT Framework in edge computing using Gateway and RAID 6

1.1 Master Accelerator (MA)

1.3 Memory Management Unit (MMU)

2 Memory Management Units (MMU):

3 Comparative Analyses

4 Conclusion and Future scope

References

Additional Declarations

Status:

Version 1