Device structure and simulation
Fig. 1a shows a schematic diagram of SBRAM in the form of a cross-point vertical array, representing one of the possible candidate array configurations, along with a cross-sectional view of the unit cell. Our device features a Si nanowire structure consisting of physical n-p1-p2-n+ layers, with the p2 base layer exceptionally made of silicon-germanium (SiGe) material. The germanium content (x in Si1-xGex) is set to 0.3 to minimize the lattice mismatch, enabling the deposition of a dislocation-free layer18-21. The channel area of the vertical nanowire is 20×20 nm2 for high-density array configuration. The anode electrode is made of a Schottky metal with a Schottky barrier height of 0.5 eV, and is designed to prevent the reverse influx of carriers. The doping level of the n+ region is 1020 cm−3. The doping level of the n-base is 1018 cm−3, which prevents Schottky tunneling and ensures the sufficient impact ionization effect. The doping level and length of the p1-base are 5×1017 cm−3 and 50 nm, aiming to achieve low standby power, as will be discussed later. In the p2-base, the doping and length are1018 cm−3 and 50 nm, considering the margin for charge storage.
The SBRAM cell was simulated using Sentaurus technology computer-aided design (TCAD)22. Fig. 1b shows the calibration results using hysteresis experimental data from TRAM and biristor—both Si-based floating body memories23,24. This ensures the reliability of our simulation data. The calibration of TRAM considers both the energy barrier height and the resulting hysteresis window, both of which highly dependent on various gate biases23. For biristor calibration, the generation of charges through impact ionization and the resulting effects on the floating body is emphasized24. The physical parameters of recombination model were adjusted, and interface Shockley-Read-Hall (SRH) model was also adopted to reflect the data retention characteristics of real memory devices, which are significantly affected by junction and interfacial defects25-26. A general drift-diffusion transport model, applied with Fermi-Dirac distribution, was used. The Philips unified mobility Model was applied to account for carrier scattering and doping-dependent mobility degradation27. The Oldslotboom bandgap narrowing model was adopted to consider the bandgap reduction in the heavily doped region28. An Avalanche generation model was used to calculate the generation of storage carriers through the impact ionization effect29. The voltage pulse width of all operations except the erase operation was set to 2 ns, which specifically surpasses the access speed of state-of-the-art 1T-1C DRAM memory30. The erase voltage pulse width was extended to 16 ns to reliable erasure of stored data.
Basic Operational Characteristics
Fig. 2a shows the asymmetric hysteresis characteristics of anode current-anode voltage (IA-VAC) and anode current-gate voltage (IA-VGC) in the program and erase operations of SBRAM. When voltage pulses with VAC = 1.6 V and VGC = 0.6 V are applied for the program operation, latch-up occurs, and IA increases sharply. Then, a wide counterclockwise hysteresis loop is formed, indicating an increase in the potential of the p-base. Subsequently, voltage pulses with VAC = −1.2 V and VGC = 0.6 V are applied for the erase operation. Unlike the program operation, no hysteresis loop is formed because the Schottky barrier prevents latch-up under reverse bias. The IA level returns to its initial state, which means the increased potential decreases.
The energy band diagrams and hole densities are extracted during the program and erase operation steps to closely analyze the changes in the base potential resulting from the memory operations (Fig. 2b-e). Firstly, Fig. 2b shows the program latch-up process. When the VGC increases to 0.6 V, the energy barrier height of the p-base decreases. When the VAC of 1.6 V is applied simultaneously, electrons from the n+ region flow into the base region over the decreased energy barrier height. The injected electrons cause high-speed impact ionization in the high electric field area of the n-p1 junction, which generates electron-hole pairs. While maintaining the program voltages, the generated holes mainly accumulate in the p2-base composed of SiGe with a valence band offset. The accumulation of holes increases the potential of the p-base, facilitating the influx of electrons that lead to impact ionization from the n+ region to the base region. This sequence of processes activates the positive feedback, resulting in the program latch-up. As a result, the device transitions from a high-resistance state (HRS) to a low-resistance state (LRS). Fig. 2c shows a comparison between the energy band diagrams of the equilibrium and programmed states. In the equilibrium state, the device shows a high energy band height in the p-base, indicating the HRS. Conversely, in the programmed state, the device shows a low energy band height in the p-base, indicating the transition to the LRS. This is because the generated holes by the program operation are maintained for a certain period, thereby increasing the potential of the p-base.
Next, Fig. 2d shows the erasing process of the stored holes in the program operation. When the VGC increases to 0.6 V, an inversion layer is formed in the p-base. The stored holes are depleted as they recombine with electrons in the inversion layer. However, the erasing method, where only VGC increases without adjusting VAC, may cause a problem in that electrons from the inversion layer flow into the n region, thus reducing the built-in potential. To preserve the built-in potential of the floating n-base, the VAC should be decreased to −1.2 V. Fig. 2e shows the comparison between programmed and erased states with energy band diagrams. In the erased state, the hole density of the p-base returns to the equilibrium state, and thus the potential decreases. The increased energy band level, resulting from the reduced potential, indicates the transition of the device from LRS to HRS. What is important to note about this memory operation is that the Schottky barrier blocks the thermionic emission of electrons that cause the impact ionization in reverse bias. This blocked reverse current suppresses the generation of excess holes and thereby ensures the reliability of the erase operation. Additionally, unidirectional conduction can block the sneak current paths that can cause leakage currents and readout errors in the cross-point array operations.
Bandgap Engineering for Low Standby Power Consumption
Fig. 3a shows the stored hole density as a function of the standby time after programming. Although the p2-base has better retention characteristics than the p1-base due to its valence band offset, which effectively suppresses hole diffusion, the stored holes completely disappear after a standby time of approximately 10 ms. As such, capacitor-less floating body memories have poor retention characteristics compared to conventional 1T-1C DRAM, so more frequent data refresh operations may increase latency during data retrieval and consume additional power in most floating body memories8-12. Thus, it is necessary to apply a holding voltage (Vhold) to ensure continuous retention characteristics by compensating for the loss of stored holes without the refresh operations. Fig. 3b shows the quasi-static IA-VAC hysteresis curve for a grounded gate, i.e. VGC = 0.0 V, to determine the minimum Vhold that can maintain the stored holes with minimal standby power consumption. When the VGC is grounded, latch-up is closely related to the open-base breakdown of the bipolar junction transistor (BJT)31. The memory state according to latch-up can be explained by the amplification of IA through two factors: current gain (β) and multiplication factor (M), which is expressed in the following Eq. (1):
Where the floating base current (IB) consists of stored holes formed through impact ionization. The β, which is related to retention characteristics, is used as a criterion for how well the stored holes can be maintained. The M, associated with the impact ionization rate, is used to determine how effectively the excess holes can be transferred to the p-base region. According to Eq. (1), it can be seen that latch-up occurs under the condition, i.e. (M−1) ⋅ β = 1 where IA momentarily diverges. The latch-up voltage is 2.9 V, which forms a positive feedback system consisting of hole generation and retention. Then, the device switches from HRS to LRS. After the latch-up, the high IA is observed in a high voltage region for (I) VAC ≥ 2.6 V. This is because a high electric field is formed, increasing the electric field at the n-p1 junction and amplifying excess holes. The stored holes in the p-base lower the energy barrier height, facilitating the flow of electrons to the p-base. As more electrons flow into the base region, this process continues to repeat, increasing β. In other words, when the VAC corresponding to section (I) is applied after latch-up, the device shows LRS. Next, it can be seen that the IA in section (II) 1.1 V ≤ VAC < 2.6 V is significantly lower than that in section (I). This is the result of band offset engineering, where the p-base is designed by splitting it into p1-base (Si) and p2-base (SiGe). Moreover, a particularly notable aspect is the gradual slope of the IA in section (II), characterized by 523 mV/dec. This means that the device has a significant margin for determining the Vhold.
Fig. 3c shows the energy band diagram and hole density at VAC = 1.1V, the voltage within section (II), providing a comprehensive analysis of the low-level IA resulting from band offset engineering. As VAC decreases, the number of generated holes decreases due to weak impact ionization, which is characterized by low M and β values. The generated holes are not evenly distributed over the entire p-base; instead, they are accumulated locally within the p2-base. This occurs because the p2-base with valence band offset has better hole retention characteristics than the p1-base. The p2-base accumulates most of the generated holes in the valence band offset region, thereby lowering the energy barrier. In comparison, the p1-base, where few holes are stored, has a high energy band level, forming a hump that prevents the inflow of electrons. Thus, this heterojunction adjusts the positive feedback system to have a low IA by physically separating the n-p1 junction and the p2-base where impact ionization occurs. As a result, setting the Vhold to 1.1 V can minimize standby power consumption, thereby maintaining the stored holes at a very low standby IA of 35.7 fA.
Fig. 3d shows the stored hole densities as a function of standby time, confirming the persistent hole retention characteristics when the Vhold of 1.1 V is applied. As the standby time increases, the majority of the holes stored in the p1-base decreases, while the hole density stored in the p2-base converges to 8.4×1017 cm−3. This result highlights the stable maintenance of stored holes even under steady-state conditions, in contrast to the case in Fig. 3c where Vhold is not applied. Fig. 3e shows the program and subsequent read operations at Vhold of 1.1 V to verify the normal read operation under the ultra-low current retention condition. The standby time between them is 10 s, which is sufficient for the memory to reach a stable steady state. After the program operation, the standby current converges to an ultra-low level of 35.7 fA. Afterwards, the read current rapidly increases to a level where the switched state can be normally detected. These results indicate that our device can maintain the detectable programmed state with the ultra-low standby current level, without a requiring refresh operation.