A high-performance time to digital converter for dToF LIDAR applications

doi:10.21203/rs.3.rs-4250377/v1

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A high-performance time to digital converter for dToF LIDAR applications

https://doi.org/10.21203/rs.3.rs-4250377/v1

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As the resolution and conversion speed of Time-to-Digital Conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy. This paper presents a high linearity, low power consumption, and wide dynamic range TDC that has been achieved based on the SMIC 180 nm V3E BCD process. Compared with previous research methods, the proposed phase arbiter structure can eliminate sampling errors and improve the linearity of TDC. The preprocessing circuit can eliminate fixed errors caused by Start and Stop signal transmission delays. Post-simulation results show that the TDC has high linearity, with ranges of DNL and INL being − 0.76LSB < DNL < 0.89LSB, and − 0.59LSB < INL < 0.73LSB, respectively. The highest resolution is 150 ps, dynamic range is 2.5 ms, and the power consumption is 1.73 mW. The overall system architecture of TDC is very simple, and it can be applied to dToF LIDAR to measure photon flight time, capable of measuring a range of up to a kilometer, with an accuracy of 2.25 centimeters, high linearity, and without any post-processing or time calibration.

Time-to-digital converter

TDC

LIDAR

linearity

resolution

sampling error

TDC is an important component of dToF LIDAR systems [1], and an on-chip integrated TDC is usually used to accurately measure the time in flight of photons [2]. The LIDAR system emits photons and receives the returned photons through a photodetector, generating Start and Stop signal pulses, respectively. Photon flight time is equal to the time interval between the Start and Stop pulses, and the photon flight time is converted into a digital code by the TDC to indicate the distance to the target. At present, the dToF ranging method has become a popular future development direction of 3D depth vision technology by virtue of its long ranging distance and better low-light performance, while the performance of TDC directly determines the ranging accuracy and error of dToF LIDAR [3–6].

Common types of TDCs are [7]: (1) Clock-period countertype TDC, which use a fixed-frequency clock to drive the counter counting principle, and the period T of this clock is the smallest unit of time quantization, with the advantage of a simple structure and a large dynamic range, and the disadvantage of a limited accuracy. (2) Delay lines type TDC, the delays line in series CMOS gate delay as a unit, the minimum resolution depends on the gate delay time, usually in the 180nm process, an inverter transmission delay is only 50 ps or so, this structure overcome the traditional countertype TDC in the resolution index is limited by the clock frequency problem. (3) Vernier TDC, the implementation of the functional principle is similar to the vernier caliper, which will be based on the gate-level delay lines TDC extended to two delay lines. The resolution is equal to the difference between the delay time of the fast delay line unit and the slow delay line unit, which can achieve a resolution lower than the gate delay. However, it is susceptible to process and environmental influences, resulting in different delay times for each delay unit, and ultimately the difference between the two delay lines is larger, resulting in poorer linearity of the TDC [8]. (4) Countertype + delay lines type TDC, this hybrid structure of multi-stage measurement TDC, can improve the measurement accuracy while expanding the dynamic range [9].

In summary, the combination of each single-mode TDC and segmented TDC constitutes a wide dynamic range and high-resolution TDC, and in the multi-segment TDC system architecture. The time to be measured in the lower segment TDC is actually the remaining time of the higher segment TDC, which is in essence the quantization of the time to be measured by a variety of TDCs with different resolutions. The key to realization is the articulation between the TDCs of each segment, that is, to satisfy the phase matching between adjacent segments [10]. Based on the foundation of multi-segment TDC realization, many novel structures have been born. For example, the ring oscillator type TDC, which has the advantages of simple structure and robustness [11], is the most suitable type of TDC to be integrated into large-scale arrayed LiDAR chips.

In this paper, a high-performance gated ring oscillator-type TDC for LIDAR applications is proposed. Based on gated edge triggering, a phase arbiter circuit is used to sample and hold the corresponding 16-phase rising edge positions in the VCRO at the moment of the onset of the Start and Stop pulse signals, which effectively avoids the sampling error and improves the linearity of the TDC. Section II discusses the proposed TDC architecture and its operating principle. Section III describes the circuit implementation and design ideas. The simulation results are further analyzed in Section IV. Finally, Section V draws conclusions.

The TDC, at the circuit level, uses a ring voltage-controlled oscillator-based TDC structure to quantify the time-of-flight, which is more compact and simpler compared to other types of TDCs (for example vernier-type TDCs) [9, 12]. The block diagram of the gated ring oscillator type TDC module proposed in this paper is shown in Fig. 1. The system mainly consists of a voltage-controlled ring oscillator (VCRO) circuit, preprocessing circuit, counter, encoder, sampling circuit, and parallel-to-serial conversion output (PISO) module.

The core of the TDC is an 8-stage pseudo-differential voltage-controlled ring oscillator with VCRO as shown in Fig. 1, which is controlled by a PLL generating a stable Vctrl voltage to obtain the desired oscillation frequency [13], thus expanding the frequency tuning range and improving the overall TDC measurement performance. Firstly, the Start signal, Stop signal, and Reset signal go through a preprocessing circuit to generate the enable signals Ron, R1 and EN to control the other modules to work. The fine resolution of the TDC is determined by the 16 uniform phases (P1-P16) generated by the VCRO, and the minimum resolution is equal to the magnitude of the time of one phase difference, defined as P; the sampling circuits are used to control the frequency of the TDC at the moment when the Start and The preprocessing circuit samples and holds the 16 split-phase clocks at the onset of the Start and Stop signals, respectively, to form a 16-bit binary code with phase position information, which is encoded by the encoder and converted into two 4-bit phase signals. The P16 phase output is followed by a 20-bit asynchronous counter for coarse counting, and the size of the coarse counting time for a cycle is equal to 16*P. The 28-bit phase signal is output via PISO to peripheral equipment. The overall system architecture of the TDC is very simple and does not require the use of an FPGA or processor to perform the time-to-digital conversion.

In order to achieve smaller resolution, accurate sampling of the Start and Stop signals at the moment of their onset is required to correspond to partial phase clock phase information within the VCRO [10]. Conventional sample-and-hold circuits consist of switching devices, capacitors, and operational amplifiers. The response speed and accuracy of this circuit structure are not suitable for phase sampling of TDC [14]. The sampling circuit proposed in this paper is described in detail in Section III. Figure 2 illustrates the timing principle of the TDC quantization process in this design. Start and Stop pulse signals arrive at the time of the sampling circuit samples the 16 split-phase clock phases to generate a 16-bit binary code consisting of 0 or 1. The encoder then converts this special 16-bit binary code into a 4-bit code that represents the fine resolution results, which are passed to the PISO output. The counter is incremented by 1 when the VCRO cycles through 16 phase changes. To be measured time interval expression

T = COUTER*16*P + t2-t1, (1)

where COUTER is the counter reading, t2 and t1 are equal to the encoder 2 and encoder 1 output code corresponding to the decimal value and P product.

The VCRO uses a tail-differential pair structure to effectively suppress the effect of power ground noise [15]. The structure of this design is to add MN1 and MP3 tubes to the conventional pseudo-differential structure, as shown in Fig. 3. Among them, the MN1 tube is used as an enable switch to achieve the global gating function, and the MN1 tube is in a saturated state when it is on. So, it can be regarded as a current source, which isolates the VCRO from the ground, and it can reduce the power supply ground a noise interference. MP3 tube is used in the adjustment of the oscillation frequency of the VCRO. In order to compensate for the oscillation frequency affected by the PVT, the VCRO control voltage is generated by the PLL. By adjusting the gate voltage Vctrl of the MP3 tube, the frequency of the oscillator is locked at 416 MHz. As shown in Fig. 3, a 16-channel high-frequency split-phase clock (P1-P16) can be obtained by connecting eight pseudo-differential units head-to-tail, and the split-phase clock divides the oscillation period into 16-time intervals to achieve a resolution of 150 ps. The split-phase clock has low jitter and low phase noise. These characteristics are critical to the overall linearity of the TDC [16]. Spectre simulation results are shown in Fig. 4. The phase noise is -100.64dBc/Hz, -124.88dBc/Hz at 1MHz and 10MHz respectively, and the split-phase clock jitter is at 3.24ps.

The Vctrl voltage provided by the PLL controls the oscillation frequency of the VCRO and thus the resolution of the TDC [17]. The variation of Vctrl voltage concerning the oscillation frequency of VCRO is scanned by simulation after the tt process angle at 25°C. The simulation results are shown in Fig. 5, the changing relationship between the oscillation frequency and resolution of VCRO and Vctrl voltage, the average gain of VCRO during the changing of Vctrl voltage in 0V-1.3V is 323MHz/V. To obtain the Vctrl control voltage, it is necessary to provide a voltage after locking the frequency of the PLL; the PLL's oscillator structure and the TDC's VCRO keeping in line can improve the linearity of the TDC's VCRO by more than 99% linearity [18]. This control voltage given by the PLL can effectively compensate for the effect of PVT variations on the TDC resolution. By adjusting the Vctrl voltage (0V-1.3V) the corresponding resolution variation can be achieved in the range of 148.8ps-626.4ps. as shown in Fig. 5.

As the TDC time resolution and sampling clock frequency continue to improve, the bit error rate (BER) increases, which seriously affects the accuracy of the TDC [10, 19]. The resolution of the TDC is determined by the high-frequency split-phase clock frequency and the sampling circuit. In this paper, the proposed a phase arbiter circuit structure for the sampling circuit of the TDC, and circuit structure is shown in Fig. 6. The circuit is a completely symmetric topology, with good matching, which allows the sampling circuit to be less sensitive to changes in the external environment. The circuit is composed of a comparator, a reset circuit, and an edge detector. Compared with the traditional comparator structure, there is one more M3 tube, which can reduce the influence of circuit parasitics, increase the matching degree of the circuit, and improve the speed and accuracy of the comparator. The TDC quantizes the interval between the Start and Stop pulse signals using the rising edge as a reference, so the phase arbiter adopts the rising edge detection. The circuit works as follows: the left and right sides of the A and B ports are input to be detected phase signals; RESET is active at a high level, the phase arbiter works at a low level, and not only plays the role of reset but also shuts down the input of the signal to be detected at a high level, which effectively reduces the overall power consumption of the circuit. Add a buffer between nodes a and b and output ports OUTA and OUTB, which can reduce the impact of the load circuit, but also improve the ability to drive the next level of load.

Table1 Transistors size of the phase arbiter circuit

Transistor name	Parameter(W/L)
M1、M2	2\(\mu\)/0.2\(\mu\)
M3	0.22\(\mu\)/0.8\(\mu\)
M4、M5	1.2\(\mu\)/0.18\(\mu\)
M6、M7、M8、 M9、M10、M11	0.4\(\mu\)/0.2\(\mu\) 0.4\(\mu\)/0.2\(\mu\)

The transient simulation results of the phase arbiter are shown in Fig. 7. Given the minimum interval of 1ps between the A and B pulse input signals, when the A signal is ahead of B, it can be seen that the node Pulse A is pulled down earlier than the Pulse B signal; at the same time, the levels of nodes a and b are also raised, but the Pulse A potential is pulled down earlier, and the M1 tube is switched on first, so that the potential of the point a is pulled up faster than that of the point b. The level of nodes a and b is also raised. When the voltage at node a exceeds the threshold voltage of the MOS tube the M5 tube is switched off, M9 is switched on and the level at node b is pulled to ground, completing a phase arbitration. The result of this phase arbitration is that the OUTA port outputs a high level and the OUTB port outputs a low level, and the converse holds true for the B signal exceeding the A signal.

In order to achieve the accuracy of TDC quantization without subsequent correction processing [10], a preprocessing circuit is proposed. The circuit has a simple structure, as shown in Fig. 8, and the preprocessing circuit consists of three D flip-flops with a reset function and a buffer, which implements the function of preprocessing the Start and Stop signals to generate rectangular pulse signals with edge information for the enable control of other sub-modules of the TDC. This crossover structure reduces the difference between the propagation delays of the Start and Stop signals in the circuit and improves the accuracy of the TDC measurement without the need for subsequent time correction processing. The operating timing diagram of this preprocessing circuit structure is shown in Fig. 6. When the rising edge of the Reset signal arrives the Ron and EN signals go high, the MN1 tube of the VCRO is turned on when Ron goes high, and the power supply to the ground forms a path oscillator that begins to oscillate and quickly stabilizes at the frequency locked by the PLL; EN high level on the counter, encoder and sampling circuit for reset, at this time the three modules are in the off state, the circuit power consumption is very low. When the rising edge of the Start signal comes to the time, the R1 signal becomes high, EN signal becomes low, at this time the counter and encoder are in the pending work state; the sampling retention circuit at the end of the reset immediately after the arbitration of the phase of the 16 phases in the VCRO and the R1 phase, resulting in a special 16-bit binary code. Referring to the timing diagram in Fig. 2, it can be known from the arbitration result that the R1 phase is in the VCRO 16 phases in the most coincident phase, which is a result of fine resolution. In the TDC system proposed in this paper, we are the 16 split-phase clock signals of the VCRO are given to the side of the 16 phase arbiters, and the B side of the phase arbiter is connected to the R1 signal. When the phase of the split-phase clock is ahead of the R1 phase, the arbiter outputs a high level, and vice versa outputs a low level, at which time we get a special 16-bit binary code. For example, Fig. 2 shows the Start signal comes temporarily corresponding to the P3 phase, the output of the phase arbiter is 1111000000000000, where the first one is 1 and the second one is 0 at the phase is the closest to the R1 phase position. And then after a specific 16 to 4 encoder encoding can output the result of fine resolution. When the rising edge of the Stop signal when the Ron and R1 signals become low, at this time the MN1 tube is off, VCRO stops oscillating, and can maintain the level of the phase at this time, due to the use of differential pairs of structures, will get a 16-bit binary code, in which there are 8 consecutive 1 and 8 consecutive 0 (Consecutive in this context includes both the first and the last). Again, the desired result is at the position of the 1 then 0 junction. The output is then directly encoded using a 16 to 4 encoder. Finally, the PISO transmits the 28-bit digital signal to a peripheral device, thus completing a TDC conversion.

The encoder circuit consists of an SR latch, or gate, and gate, and a non-gate, as shown in Fig. 9. The function it implements is to convert the special 16-bit binary code output by the arbiter into a 4-bit binary code that can represent the fine-resolution result, which is then sent to the PISO output. The encoder circuit structure is shown in Fig. 9, and the encoder resets the SR latch when EN is high and encodes normally when EN is low. Firstly, the result of the arbiter output is stored in the latch to eliminate the crosstalk between the circuits and improve the stability of the circuit. The combination of and gate and non-gate is used to determine the position of the “first 1 and then 0”, and then converted into a binary code used to represent the result of a fine resolution.

Parallel Input Serial Output Shift Register (PISO) circuit, which is mainly composed of and gate, or gate, non-gate and D flip-flop, the principle of the circuit is shown in Fig. 10.The inputs of the PISO are provided by the encoder and the counter, and the data are input in parallel to each D flip-flop when the Load signal is low, and the outputs are collected serially in the outputs of end-flip-flops when the Load signal is high. In this PISO, the first and last two bits are used as flag bits, D1 is connected to the low level D30 is connected to a high level for detecting whether the code is transmitted properly or not; where D2-D9 are connected to the outputs of the encoder, and D10-D29 are connected to the outputs of asynchronous counters, and CLK is the clock for communication with the external.

The TDC chip design is fabricated using the standard SMIC 0.18um V3E BCD CMOS process, the overall area is shown in Fig. 11, the chip layout area is 150um*115um, and there are mainly preprocessing circuits, VCRO, encoders, counters, and PISO circuit modules, which do not include the peripheral circuits connected to the pin Pad. At a supply voltage of 1.8V and 25 degrees Celsius, the post-simulation results show an average current of 903.1uA and a power consumption of 1.625mW.

The test of static characteristics of TDC circuits includes dynamic range, time resolution and nonlinear error [7]. The dynamic range and time resolution can be expressed by constructing the transfer characteristic curve, and the nonlinear error can be obtained according to the transfer characteristic curve. The specific test method of the transfer characteristic curve is as follows: firstly, the time interval between Start and Stop is stepped at an interval of 2.4ns of coarse counting period, which is used to detect the dynamic range of the circuit measurement. Then a few critical times are selected as starting points and stepped in the same way with a time length of 10 ps, and then the input time intervals corresponding to the jumps in the output results are recorded, and the time intervals between the two jump points are the actual time resolution. The statistical input time interval starts from 1 ns to 200 ns, and the transfer curve of the TDC is shown in Fig. 12. The measured input time interval and the measurement time interval can maintain a strong linear relationship, in which the nonlinear error is less than one resolution of 150 ps.

In evaluating the nonlinearity error of the TDC system, differential nonlinearity (DNL) and integral nonlinearity (INL) curves were obtained as shown in Fig. 13, based on all the data obtained from the 50–55 ns resolution test. The results show that − 0.76LSB < DNL < 0.89LSB; -0.59LSB < INL < 0.73LSB, which are both less than ± 1 LSB (1 LSB = 150 ps), indicating that the TDC circuits have a high degree of linearity and a small range of error fluctuations.

Table 2 summarizes the key performance of the proposed TDCs compared to the existing techniques. The paper [1]presented in 2021 uses address latches to save the signals at the moment of Stop coming, which enables a single TDC to measure multiple events. The paper [10] does this by combining a Union Reference Counter (URFC) with an interpolated delay line to obtain high accuracy and wide dynamic range. However, it employs a D flip-flop for the sampling circuit, which has poor sensitivity on high-frequency clock phase sampling and is prone to nonlinear errors. The paper [14] adopts a comparator structure circuit to do the sampling, which effectively reduces the occurrence of sampling error and improves the linearity of the TDC, which also requires time correction processing, has a more complex structure, and the dual delay loop is susceptible to PVT. The paper [20] proposed a Gated Ring Oscillator (GRO)architecture to reduce the area and power consumption. Nevertheless, it adopts a D flip-flop for the sampling with a resolution of 1.76 ns at 1KS/s sampling frequency. There is also a paper[21] using a D flip-flop to do the sampling, limited by the D-trigger, the minimum resolution is only 36.2 ps, if the phase arbiter circuit proposed in this paper, the resolution can be further improved. Compared with previous work, the TDC circuit designed in this paper achieves a large dynamic range with high linearity while maintaining a relatively small-time resolution. Meanwhile, other performance parameters of the TDC such as area and power consumption are controlled within reasonable limits.

Table 2

Key performance comparisons of the TDC
Parameter	This work	[10]	[14]	[1]	[20]	[21]	[2]
Technology node/nm	180	65	180	65	130	40	150
Architecture	VCRO+ TDC	URFC+ Vernier	Vernier+ TDC	DLL+ TDC	GRO-Based	Branching	GRO
Dynamic range/us	2500	2.5	210	0.64	1.76	0.148	0.053
Resolution/ps	150	19.5	17	97.65	1760	36.2	210.2
DNL/LSB	-0.76 ~ 0.89	-0.94 ~ 1.67	-0.4 ~ 0.5	-0.4 ~ 0.6	-	1.3	1.28
INL/LSB	-0.59 ~ 0.73	-2.75 ~ 2	-1 ~ 0.4	-0.4 ~ 0.7	-	3.61	1.92
Power(W)	1.625m	51.4m	-	-	45.85n	0.28m	-
Area(um²)	17825	432000	1822500	-	-	43000	402.7

In this paper, a new phase arbiter and preprocessing circuit technique is proposed and applied to a TDC design, which can achieve high linearity, low power consumption and no subsequent time correction. The TDC chip is designed using the SMIC 180 nm V3E BCD process, and post-simulation results verify the effectiveness of the technique. The simulation results show an average current of 903.1uA at a supply voltage of 1.8V, a power consumption of 1.625mW, a minimum resolution of 150 ps, a dynamic range of 2.5 ms, and high linearity. This TDC for dToF LIDAR photon time-of-flight measurement has a simple architecture and can measure distances as low as 2.25 cm and as high as thousands of kilometers, making it ideal for use in applications such as rangefinders, dToF LIDARs, UAVs, and robotic advanced pilot assistance systems.

Author Contribution

Bangtian Li: Software, Validation, Writing - review & editing, Writing the original , Validation, Writing the original draft. Liying Chen: Supervision, Conceptualization,Methodology, Project administration, Software. Chuantong Cheng: Validation, Writing - review & editing.

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No competing interests reported.

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A high-performance time to digital converter for dToF LIDAR applications

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Abstract

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1 Introduction

2 Gated ring oscillator type TDC and principle of operation

3 TDC circuit design and implementation

4 Analysis and discussion of simulation results

5 Conclusion

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Author Contribution

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