Three-dimensional simulations of NS-TFET are done using COGENDA-TCAD software [24]. The physical models such as the DD model, Lombardi mobility model, Kane's BTBT model, and SRH model are evaluated at each mesh node using TCAD software. The performance metrics of vertically stacked NS-TFET device has been discussed in this section.
4.1 Triple nanosheet
Gate all-around devices provide little room for carriers to drift when the transistor is in ON state [25]. The stacking of nanowires increases the effective width and allows the carriers to flow, but the increased device capacitance along with surface roughness decreases the speed of carriers [26]. Stacking thin nanosheets atop one another enhances the effective width and hence provides larger room for carriers to flow. This further enables the large drive current while maintaining constricted control of the leakage current [25–26].
We have performed the simulations for vertically stacked single, double and triple NS-TFETs at the drain to source voltage (Vds) of 0.65V. The plot of drain current of single nanosheet (Id_1ns), double nanosheet (Id_2ns), and triple nanosheet (Id_3ns) is depicted in Fig. 3. The results show that ON-current increases exponentially in the case of double and triple NS-TFETs as compared to single NS-TFET. The drain current of Id_3ns and Id_2ns is observed to be 2.0168 and 3.03 times higher than Id_1ns respectively. Ion/Ioff ratio in triple-stacked NS-TFET is 9.557 times that of single NS-TFET while with double-stacked NS-TFET, it is observed to be 4.73 times high. Hence, three-layered NS-TFET exhibits superior performance in terms of drive current
4.2 Energy Band Diagram
The NS-TFET exhibits similar behavior to that of n-TFET on the application of constant drain voltage. In NS-TFET, an interband tunneling conduction mechanism has been incorporated. In the OFF state of the p-type extended source of NS-TFET, very few electrons are available at the conduction band of the source for injection into the channel. This results in negligible movement of carriers and hence poor leakage current. With variation in the gate voltage, the energy band of the channel varies relative to the extended source. From Fig. 4, it is evident that at saturation voltage of Vds = 0.65V with positive gate to source voltage (Vgs > 0V), the valence band of the extended source is aligned with the conduction band of the channel. The carriers tunnel through the potential barrier between the valence band of the extended source and the conduction band of the channel. These charge carriers present in channel drift towards the extended drain (ext_d) to produce drain current.
4.3 On Current and OFF current
Figure 5 depicts the transfer characteristics of NS-TFET. In the off state of TFETs with zero gate to source voltage, the movement of charge carriers from the valence band of the extended source region into the channel region is hindered due to large tunneling barrier width. Hence, the leakage current is extremely low. In the off state, linear leakage current(I_Lin) is of the order 10-16A at gate voltage Vgs = 0V with drain voltage Vds = 0.10V. On application of positive gate voltage, bandgap modulation takes place as shown in Fig. 4. With the gradual increase in gate bias, the bands of the channel are lowered; thus enabling more electrons to tunnel from the valence band of the extended source into the conduction band of the channel. The tunneling barrier width is reduced near the extended-source channel region leading to a steep increase in the drain current. At saturation voltage of Vds = 0.65V, leakage current is of order 10-14A. The saturation ON current (I_sat) reported is 1.26x10-5A at Vds = 0.65V with Vgs = 1.2V. Thus, the Ion/Ioff ratio for three-layered NS-TFET is 1.101x1011. This high Ion/Ioff ratio is desirable for high-performance nanoscale devices.
Table 2
Figures of merit of NS-TFET
Figures of Merit
|
Values of n-NS-TFET
|
Values of p-NS-TFET
|
Leakage current
|
1.0144x10− 16A
|
1.16147x10− 16A
|
Ion/Ioff ratio
|
1.101x1011
|
9.378x1011
|
Threshold Voltage
|
0.402V
|
0.400680V
|
DIBL
|
10.5
|
11.4
|
Subthreshold swing
|
23mv/decade
|
23.786mv/decade
|
4.4 Sub-threshold swing and DIBL
The main premise of designing NS-TFET as an alternative to NS-FET is due to its refined subthreshold swing. NS-FETs operate on a thermionic injection mechanism and thus have a thermal limit of 60mv/decade [27]. In NS-TFETs, the BTBT conduction mechanism is utilized. NS-TFET offers desired steep SW of 23mv/decade at low Vds = 0.10V with the desired ON-state performance. For this subthreshold regime, the threshold voltage is 0.402 V and negligible Drain induced barrier lowering (DIBL) of 10.5 is found. SW gives a higher Ion/Ioff ratio and thus makes itself apt for faster switching circuitry. Table 2 represents the performance metrics of NS-TFET in terms of threshold voltage, SW, DIBL, etc.
4.5 Ambipolairty
The transfer characteristics of three-layered NS-TFET under different doping concentrations have been represented in Fig. 6. It is evident from the figure that NS-TFET shows its ambipolar behavior when it is subjected to the negative gate to source voltage(Vgs < 0V). The electrons tunnel from the channel to the conduction band of the extended drain and thus results in the current flow of the same polarity and hence behave as p-type. This behavior is not desirable in digital circuitry where tunneling between channel and drain is curbed [28–30]. The best results are observed for the doping concentration of 1017cm−3. It is evident that with the decrease in the doping concentration of drain, an ambipolar current is reduced up to a considerable amount. The depletion width of the drain side increases due to lower drain doping concentration. As a result, ambipolar current reduces.
4.6 Transconductance(gm),Transconductance generation efficiency(TGF) and Total Gate Capacitance(Cgg)
Transconductance (gm) is a performance metric, which reflects the device efficiency in terms of effective input voltage conversion into output current [31]. It is described by first-order differentiation of drain current with reference to the gate to source voltage [32].
![](data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAASYAAAA1CAYAAADs8UZbAAAHM0lEQVR4Ae2d4XHrIBCE1Uu6UAPphJmU8v7RRTqggZTBpJZ7s6CTMUKWsHBs5PWMJwrCCH2KN8dxHIPwRQIkQAIvRmB4sf6wOyRAAiQgFCb+EZAACbwcAQrTnY9kGIjuTnT8GAlsEjjBt8uLM6NAKPAejROf3LYzsXw+b9OzScXKQwpTJTBWJ4EKAt0Lk7NW3Kw1UaTGTHy8hXCNkhVXYFpWpTAtmbCEBFoR6F6YliC8WGOXVpNxy6oHSihMB+DxoySwQeCEwiTijJGLDDkxwyCNdSkMGzfY8jQJkMCdBPoXJu/EjOpHGsU4Lx7DOwXirYyNh3FomhaTAuZPEmhPoG9hckbGYA2pk8mLs0bGZCgX/Evj9dCuBUYKUwuKbIMEygQ6FqY4RMsd3SJerFV7yYsdB1nWKcOoKaUw1dBiXRKoI9CvMDkjw5D6kqYb91YuuvSYYRyuRGGq+0NjbRKoIdCtMJWHaNczcuU6KZ5oUQ1XnvFSWfqZeExhWjJhCQm0ItCtMEmwmJLYpOAEz35HwOVW8JIzyxm7UllGnMKUAeGvJNCQQL/CJCIeju4p4nsYzRxoGQMqdaZukGuLCB+cZvJGK1ZDC0plN0BTmG7A4SkSOEiga2G6794hSpOIIZQgDONKZbdbpzDd5sOzJHCEwNsJE6wpHd3hGLpUKtuCSmHaIsTzZyXw8fGxuLV///5Jqfzr60t+fn4W9bcK3k6YNCrcOxssJ4hUqWwTHLMLbCHi+RMSwD/kktB8fn6GmerSOQjW9/d3FY0qYfJTQCM6l743HcxVXXps5eh/ihHi1oxiQ6R4XOSLqHEt2+oFLaYtQjx/NgKwfkoCAzFCOcQJdUqv2u/LfmHSWbBpKT9E6siK/TwdSSp04fhqCr90q88tqwX93N7y6iRwjMDv7+9q7J6KEcSpNJzDlTHUw3vva6cwFSKo1wIc916583oUps4fILtfRUAtotKHUsHB96I0nEMZLKq9ryphwrR7WJXmXVjqsZiG33vVO+sFSyobRv5lWdptClNKg8dnJwDxUcsovVcITv4dXKu3Zk2l7enxTmEKQUNXq/hHe50pUhvc+5NDub2kWI8Enk9gTZhSawm9hGVV+qcNAXuQMDkxyar956N6bg9K8J/bI16dBB5HoDSUg98pFyb0AN8N1E9fDxrKxVgfXHAcjRjr5ijr+eLqcwr5jxDAGP1SL+7Dnrtfe0BhqiXG+r0TSP/m1TLKRQjDOJThnfqUIGAlEVtjsmsohxxH1secR947QZ7tkJwtU51Qz055t2FdIVZIoxnXetBpefqQOr0FdpsEqghAdHJLaG8DNcM4tLktTMWwAGSJNNkaNCzrQEI2WEoxulojq/d2vqd6FKaenhb72ooABAbDspoXLKdaQdsWJkFWyPGyWBZm2jgutknCav9gQHkrJh6IxZq0mjuoqru2bdOUtiSZvVPDLgZXRjPzaFAohanqYbHyiQjUWD+wsmqFDKh2CNM+orqsYxYoiQtjEVn9iNfWtk1xr7lcGNXvdbxPFKZHPFW2SQKRQDNhej7QQpI4NZW0c7DqGvm8KEwKlT9JoD2BEwnTZTEuMIU4qVSY5iFmG4gUpjYc2QoJlAj0K0ya2C34kvJtm+KQ7eJHgjWVD+tKOPaXUZj2s2JNEqgl0KcwbW7bdL3JZZpvqRbQWn0K0xoZlpPAcQIdCtOObZvSTS4b+pVS3BSmlAaPSaAtgf6ESSPMcw7ptk1znccto6Ew5Q+Av5NAOwLdCVOIRVrsrFuYkRvNTb9SmvQOviiEH8TMCdiLDrFaMXJ93qMuY05hyoDwVxJoSKA7Ydrctkln5MLW4WVSUdwuu6oIZuymMALEP8XD2w5zClOZLUtJoAWB/oTpxrZNCgShApcZOS3Vn/BRrc/QQbTWP6ttcCfeCwkekUB7Al0K0yEM8D9pfFNwkmv+8otYBXHSOisXo8W0AobFJNCAwHsLEwBCqBY+q5jm5ZY2qTDNCe/QxiR0eyyuBs+OTZDAaQm8nzDN+aLiM02HfciYoCtWYDXtESbBmsBB/VIizh3L7HnavzTeGAlUEHg/YQo7hE9biyNLAmbv4nScWKQLttjKaZBxI1unWkxRmKZhIHJVVcBnVRIggTKBtxSmMoq60lmYYIGFoaCXKZdeXUOsTQIksCBAYVog2VegwqSzeN7RVtpHjrVIYJsAhWmbUbGGChN8VHkOdKQUts5d+ZtCmbXiHpSfqthJFpJApwS6EiaIwSu9JaQRXsZMzUnzcD74qrA0JlpUnuO9Tr8q7PZfEuhKmP4SzP3XghjpsA7pV6JjXId897fLT5LA+xCgMLV+1ljeorqEUALsXjxZSbCkNByh9WXZHgmciQCFqfHTDFtYOS9whofwAx3O+WShcONrsjkSOBsBCtPZnijvhwROQIDCdIKHyFsggbMRoDCd7YnyfkjgBAQoTCd4iLwFEjgbgf9rVBswUHdWdAAAAABJRU5ErkJggg==)
where Idd represents current tunneling from the source terminal to the drain end. Vgs, Vds represents the gate to source voltage and constant drain voltage respectively.
Transconductance generation efficiency (TGF) is another vital parameter that determines the efficiency of NS-TFET in terms of conversion of the current into transconductance (gm) and is given by [33].
![](data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAASAAAAAtCAYAAAAOarbqAAAFuklEQVR4Ae2d4XGjMBCF6SVdqIF0opmUkn/qIh2ogZShSS178wRLlrVkfGefMfCYyRgJIaRP4nl3RfAg3EiABEhgIwLDRtflZUmABEhAKECcBCRAApsRoABthp4XJgESoABxDpAACWxGgAK0GXpemARIgALEOUACJLAZgVMIUMlRwjDI4P5CKpuB54VJgATkBKtgOcowBEl5FBuIUU1Tezj/SWBzAge3gIqkMMjC0qkCFCVvjp4NIAESOIUADTFLNXhKroKENDcSIIHtCRxcgESkJIlB4z9BQprEaHv2bAEJnJ7ACQQoS4xptIBOP9wEQAKvRaArQDmq1dD5tG5MKZJTlDBbGoOE6vYUSebmLylcrEQtVqbC44VCrxlClJiyTLHocRQ0HlSShCFKLmPMyHbtUcOFfn58fDyqOtZDAocg0BEg3Ii4Icc+1pvYiAPSepPqEneIaS6Ps+Z8v9TdWYVCnYtg8QPwQhRTmVa/SpacJndMGy9ShTOlIjkGQR9KThJ9mx/Qlu/vbwrQAziyimMRaAtQSZLmOG1rJSmNq0hVTAaJqlSOjRUqPeTFTPMlx1nU5rx7dppCV6SkKL9B6CyxCiv6GAS602qzbcbn5+fCivv5+ZkPqzXXsnQoQDMm7uyUwNvbW/0S1XluP+2cxz7m+y1bW4DsmdU9GW9Om43gbn24z1gTi+M1/gsLZJkL185aOhCEWeuWRe9MwS0MywcQA6wcE4RW0UOguvZjsvxWrgy4gG/FB6cgbQfCVkMBsjS4vycCmNd2vn99fcn7+/uiCziOL2fdIFYot7atClC1WBAfcTWNMaLLfFfMJbNEPBSoogQRM66dK/zfkzlO7VchElhEcX5o8VoDMAAeMERGRQlChEHRgaIAXaPJY69MAHMY81e3lgBBfHSuaznM/7VtpcTofv26LFrdlH8hHlP+4l8ejEhNLhsaNv9dsaBwtb8KhmvznvCJQYDK281+A9h87FOAPBGm90AA89bP85YA4X728x9pn+f7vCJAsFgQ4/GnjfmXwjSWq3GWYelq4UgVE1MZrCvrjvmrvHoa0PWbAZaPt4hs+1Vwr5Wx5blPAq9AAALiwwqYwzqf9bM1r3FveKvI9+m6AFWLxVgw89lrAoTldn9eQ8xy+nXH5rrv21Egj/zstQgDo4ODgVL3q1ee+SSwNwKY396Kgdh4YcH95vNa1pPv/1UB8haLPXl0jUw8Zz7Ycduaq1LzSd2dV3XB0GAbnFMh6naEB0hghwRuFSC1iuyX8H0CNK1yGY/J4ZusIPO8UC3QPA/P2Qxm+dtVteMkVB9/LRN0x91i00mgEui5YN7aQZzIx4r+0QVrBJIvgs06OtMDfCaoHPxSty7Xa5luXVrnvj5V+ffVaraWBG4jAIvGCgssol54w9cI8fLumy9z1QXzhZkmARI4HwFYO7Bm/nazwtU7lwLUI8N8EiCBmQCsHhvfmQ90dm4NSxxegHwQe8/L/p2xZjYJPIXALRYNGgI37VaL6fACBCDj09ytFbunjBsvQgIk0CFwCgE66gpcZ0yZTQK7IXACAWo8ALmb4WFDSeDYBI4vQPUxALpfx57G7N1eCRxegGr852DPHu11srHdJOAJHFyAxocqufLlh51pEngNAscWILpfrzHL2AoS6BA4tACtu1+tf5xt5XXoMZsESOAuAscVoDKufq26X/PbEA3HVp45zF0SIIHHEDikAI0PHl556yLECT8hFJIkfS1rK+8xjFkLCZBAh8AhBajT1yl7fO9z/SEPxIjq+0Zaeddr4VESIIH7CZxOgGAd6UvxsQ/9aeXdj5Y1kAAJrBE4nQDpL2HUHyDEL2AUvKt6fH2szVsDx+MkQAL3EzidAI3xIVg++NnoUH+Cp5V3P1rWQAIksEbgdAK0BoTHSYAEnkeAAvQ81rwSCZCAI0ABckCYJAESeB4BCtDzWPNKJEACjsAfe6om50nfEvsAAAAASUVORK5CYII=)
Figure 7a and 7b represent the variation in transconductance and TGF with respect to the gate-source voltage respectively. It is unambiguously clear that NS-TFET exhibits comparatively higher transconductance due to the hike in tunneling of carriers in the channel. For the selected value of Idd= 10− 10 A, TGF is found to be 54V− 1.
The plot of the variation of total gate capacitance (Cgg) with respect to Vgs is depicted in Fig. 7c. Cgg at Vgs = 1V is found to be 1.662x10− 17F.
p-Ns-TFET design:
The vertically stacked NS-TFET with N-I-P configuration has been designed to demonstrate its p-type characteristics. The geometry parameters are kept the same as mentioned in Table 1. Work function engineering has been implemented to match ON and leakage currents. For p-SN-TFET, the work function is kept at 4.23eV. The source has donor impurities with a concentration of 3x1020 cm− 3 while the drain has acceptor impurities having a concentration of 1017 cm− 3. The transfer characteristics of p-SN-TFET at linear voltage Vds= -0.10V and saturation voltage of Vds=-0.65V are simulated using TCAD. The simulation results of both p and n-type at linear and saturation voltage are displayed in Fig. 8. The performance metrics of p-NS-TFET are mentioned in Table 2.