A full adder is a logic circuit commonly used in digital circuits, which is used to perform the addition operation of three input bits. It includes two bit inputs and has a carry input. A full adder has two important parts: a partial sum generator and a carry generator. The partial sum generator is responsible for calculating the sum of two input bits, while the carry generator considers the carry input to determine whether to generate a carry. The full adder plays an important role in the binary adder because it can handle the carry from the previous bit to ensure the correct result when adding multiple bits. Multiple full adders can be connected together to form a larger adder, such as a 4-bit adder or an 8-bit adder, in order to realize the addition operation of larger numbers.
In previous publications, a full adder circuit designed with RTD device has been proposed [8]-[10], but the circuit is relatively complex, and the manufacturing process is not fully compatible with CMOS or BiCMOS process. Therefore, we propose a new full adder circuit based on MOS-NDR circuit, and simulate the result by HSPICE in this paper. Compared with the previous RTD-based adder, our circuit structure is relatively streamlined. Table I shows the truth table of 1-bit full adder. The three inputs Vin1, Vin2 and Vin3 represent two bit inputs and a carry input respectively. Its output is an output bit called Sum and an output bit called Carry. For a three-input adder, it can be obtained from Carry's truth table that when two or three input signals are 1, the output signal is logic 1, otherwise the output signal is logic 0 in other cases. Therefore, its Carry output is a logic circuit that performs majority function.
We use the MOS-NDR circuit and design a three-input majority circuit based on the MOBILE theory, and its architecture is shown in Fig. 3. Two circuits respectively named MOS-NDR1 and MOS-NDR2 are connected in series to form the basic structure of the MOBILE circuit, and three input NMOS switches are connected in parallel on the load device as a control for modulating the total load current. The operating principle of this circuit is analyzed as follows: (1) When the three input signals are (0,0,0), (0,0,1), (0,1,0) and (1,0,0), we must design the circuit parameters to satisfy the condition of IP,Load<IP,Driver, then the operating point is at the position of Q1 and Q2. Although the voltages corresponding to Q1 and Q2 are slightly different, they can both be regarded as relatively low levels. The load-line analysis is shown in Fig. 4 (a). Therefore, the output is at low level, which means that the output is logic "0". (2) When the three input signals are other situations, we need to design the circuit parameters to satisfy the condition of IP,Load>IP,Driver, then the operating point will be at the Q3 position. The output is at high level, which means the output is logic “1”. After correctly designing the component parameters and setting the VGG voltages of NDR1 and NDR2 to 1.28 V and 1.54 V respectively, the HSPICE simulation result is shown in Fig. 4(b), which correctly executes the majority logic function.
From the truth table of Sum in Table I, we can obtain that it is an XOR logic function for three input signals;Sum = Vin1♁Vin2♁Vin3. The output is "1" only if there is an odd number of "1"s in the input, otherwise the output is "0". We use the MOS-NDR circuit and design a three-input XOR logic gate circuit based on the MOBILE theory. The circuit structure is shown in Fig. 5. Two MOS-NDR circuits (NDR3 and NDR4) are first connected in series to form the basic structure of the MOBILE circuit. Two other MOS-NDR circuits named NDR31 and NDR32 are connected in parallel on the load side. Three NMOS input switches are connected in parallel below NDR31, and three NMOS input switches are connected in series below NDR32. We first connect a MOS-NDR element (NDR41) in parallel on the driver, and then the three input signals are first connected in series two by two and then connected in parallel under the NDR42. A total of six NMOS switches and two MOS-NDR circuits are used to form the new driver.
The load line analysis of the whole XOR circuit operation is shown in Fig. 6 (a). The total load current and the total driver current need to properly design the circuit parameters so that the relationship of IP in different input logic states needs to meet the following rules: (1) When the three input signals are (0,0,0), the magnitude of the peak current needs to satisfy IP,Load<IP,Driver, then the operating point is at the Q1 position, and the output is logic "0". (2) When the three input signals are (0,0,1), (0,1,0) and (1,0,0), the magnitude of the peak current needs to satisfy IP,Load>IP,Driver, then the operating point is at the Q2 position, and the output is logic "1". (3) When the three input signals are (0,1,1), (1,0,1) and (1,1,0), the magnitude of the peak current needs to satisfy IP,Load<IP,Driver, then the operating point returns to the Q1 position, and the output is logic "0". (4) Finally, when the three input signals are (1,1,1), the magnitude of the peak current needs to satisfy IP,Load>IP,Driver, then the operating point returns to the Q2 position, and the output is logic "1".
In order to meet the above four conditions, we design the gate width of the NMOS switch and use different VGG voltages in each NDR circuit to control the magnitude of the IP current. To realize the XOR circuit, we can control the IP current with different VGG voltages in each MOS-NDR circuit. After properly designing the device parameters of each MOSFET, we design the VGG voltages of NDR3, NDR31, NDR32, NDR4 and NDR41 to 1.52 V, 1.26 V, 1.4 V, 1.65 V and 1.26 V respectively. Figure 6 (b) shows the results of the HSPICE simulation, which correctly executes the logic function of XOR.
Figure 7 shows the simulation results of the full adder using the HSPICE program. Then this 1-bit full adder is implemented using the standard 0.18 µm CMOS technique provided from the TSMC foundry. The area of chip is approximately 0.875 x 0.89 mm2. The layout diagram of this chip is shown in Fig. 8 (a). Figure 8 (b) shows the lithography of the chip obtained by using an optical microscope, and we have marked the relative position of the NDR circuit in the figure. In order to make the output level more stable, a buffer is added to the output part. Due to the process error, there will be a little difference between the measured I-V curve and the simulated I-V curve. The advantage of our MOS-NDR circuit is that even if the IC has been fabricated, we can still modulate the magnitude of the IP current by adjusting the value of the VGG voltage. The final IC measurement result is shown in Fig. 9, which shows the result of a 1-bit full adder. A total of 7 VGG voltages are required from NDR1 to NDR41 components, and these voltages are set to 0.85 V, 1.05 V, 1.24V, 1.7 V, 1.3 V, 1.19 V and 1.26V in sequence. The voltage VS and the three input signals are all square waves with an amplitude of 1.4 V. The frequency of VS is 2 MHz. The period of the signal Vin1 is the same as VS, and the periods of the signals Vin2 and Vin3 are 2 times and 4 times of VS respectively.