Analysis, Design, and Simulation of a Very Low Voltage, Very Low Power, and Very High Speed Homo/Hetero Structure TFET-Based Dynamic Comparator in 65nm Technology

doi:10.21203/rs.3.rs-4926265/v1

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Analysis, Design, and Simulation of a Very Low Voltage, Very Low Power, and Very High Speed Homo/Hetero Structure TFET-Based Dynamic Comparator in 65nm Technology

https://doi.org/10.21203/rs.3.rs-4926265/v1

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The goal of this paper is to analyze, design, and simulate a homo/hetero structure tunnel field-effect transistor (TFET)-based dynamic comparator, which operates at very low voltage, very low power, and very high speed in a 65 nm technology. The proposed design offers a promising solution for efficient and high-performance low-power comparator design in digital applications. Through extensive simulation and analysis, the effectiveness of the proposed design is demonstrated and compared with existing designs. This study provides valuable insights for the development of high-performance, low-power comparator design in the semiconductor industry. In this paper, we present a design and simulation of a MOSFET-based dynamic comparator with improved performance in TSMC 65nm technology. The post-layout simulation is implemented in the TSMC 65nm model and validated with Design Rule Check (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX) tests to ensure the reliability and robustness of the simulation results. The time domain analysis of the post-layout simulation is also provided, which shows the circuit's reliable performance. Finally, a homo/hetero-structure CTFET model with 65 nm technology is created using the III-V model, and the proposed MOSFET-based dynamic comparator is compared with the CTFET model. To provide CMOS an opportunity to compare with CTFET, a model CTFET is developed using 65nm technology. Hence, the highest sampling frequency of 25 GS/s in PDP of 0.4325 fJ has been achieved in this article. The simulation results indicate that the proposed design has improved performance in terms of speed, power consumption, and stability.

Complementary Tunnel Field Effect Transistor (CTFET)

Complementary Metal Oxide Semiconductor (CMOS)

Dynamic Comparator

Homo-Structure

Hetero-Structure

The Comparators are one of the basic parts in most analog-to-digital converters (ADCs). High-speed, low-power comparators with a tiny chip area are necessary for several high-speed ADCs, including the Flash ADC. As compared to the scale of DC power supply (VDD) downsizing, the threshold voltage (Vth) of the transistor cannot be reduced in deep sub-micron technologies [1], whereas the designs of fast comparators face greater difficulties with the reduction of the VDD. To put it another way, as CMOS technology advances, larger transistors are needed to make up for the loss of VDD, which increases power consumption and chip area requirements in order to attain higher speeds. Moreover, at low VDD, the input common mode range is also decreased, which is significant for many ADC topologies, including Flash ADCs. To address the difficulties of low voltage design in CMOS technology, many solutions have been devised, including supply-boosting methods [2], [3], body-driven transistors [4], [5], current-mode design [6], and employing double oxide processes, which can handle greater VDD. The performance of comparators has recently been enhanced by the introduction of new methodologies that meet the demands for low power, low voltage, and high speed. Dynamic element matching (DEM) is one such method to lower power consumption and improve comparators' accuracy [6, 7]. By randomizing the error brought on by mismatches between comparator elements, DEM lowers the overall error and improves the comparator's accuracy. Voltage-mode approaches are another method for achieving great performance with low power consumption [8]. A current-starved latch is used in voltage-mode approaches to speed up and improve the power efficiency of comparators. Asynchronous logic approaches have also demonstrated the ability to support high-speed operation while preserving low power consumption [9]. Using locally generated timing signals instead of global clock distribution networks allows asynchronous logic approaches to operate more quickly and with less power. Furthermore, using cutting-edge technology, like memristors, has shown considerable potential for enhancing the performance of comparators. Comparators built with memristors have been demonstrated to operate at high speeds while using less power, improving accuracy, and requiring less space [10]. The development of high-performance comparators for low-power and low-voltage applications require a variety of advantages, including lower power consumption, higher accuracy, and increased speed. A lot of work has been put into developing transistors that can outperform MOSFETs in technologies with scales smaller than 10 nm. Tunnel field-effect transistors (TFET) have emerged as a promising option for digital circuits, among many others [11–12]. TFETs can produce a high Ion/Ioff current ratio by having a sub-threshold swing (SS) of less than 60 mv/dec [13–14]. Experimentally, a sub-threshold swing of 21 mv/dec has so far been documented [15]. TFETs have a decreased parasitic capacitance and better saturation behavior in addition to a lower sub-threshold swing, which increases the energy efficiency of digital circuits [16–18]. Compared to CMOS technology, digital circuits based on tunnel field effect transistors are more energy efficient at low supply voltages [19–21]. In contrast to CMOS technology, complementary tunnel field effect transistors (CTFET) have several advantages, which are the focus of this research. In order to design a dynamic comparator with excellent energy efficiency, homo/hetero TFET architectures in 65 nm technology are examined. Attempts have been made in this work to illustrate the design, analysis, and performance of the dynamic comparator for two models of the TFET, with homo/hetero-structures (III-V model), and a MOSFET transistor. In order to save power, a comparator that is developed for low power and very high frequency applications is presented in this study.

The sections of this paper are arranged as follows: In the second part, TFET modeling and its validation (Ⅱ-A), the TSMC 65nm model, layout implementation steps, and its simulation (Ⅱ-B), as well as the proposed dynamic comparator structure (Ⅱ-C) are described. The third part is about performance evaluation, energy consumption and speed of dynamic comparator with MOSFET transistors with TSMC 65nm model (Ⅲ-A) TFETs with homo (Ⅲ-B) /hetero (Ⅲ-C) structures. The fourth part of this paper is devoted to its conclusion and summary of it.

A. Comparator Structure

A comparator is a circuit that compares two signals and indicates which is greater. The preamplifier and latch are two parts found in comparators. The circuit schematic for the MOSFET-based comparator, which was developed with adding transistor Q2 and Q4 to the comparator structure on [22] and used in the simulations, is shown in Fig. 1. Two CMOS inverters are utilized to feed the capacitance loads in order to lessen the loading effect on the latch outputs. The comparator loses dynamic power because it has a dynamic latch and a dynamic preamplifier.

The sketch map of a dynamic comparator's transient performance is shown in Fig. 2. The dynamic comparator's transient response contains two main sections, reset and comparison. During the reset section, the output terminal voltages and the drain voltages of transistors Q5 and Q6 are all brought to VDD level by switching transistors Q8, Q9, Q12, and Q13. The comparison section starts with the tail transistors Q7 and Q16 turned on. As a result, the small signal will be transferred from the input CMOS stage (Q1 to Q4) to the cross-coupled stage (Q5 and Q6). As the output of the pre-amplifier is supplied, we will have a dual-rail input as soon as the input common mode of transistors Q2 and Q4 goes lower than the Vth of transistors Q1 and Q3. This is the first advantage of this proposed work compared to [22]. According to [22], there are three phases in the comparison section (phase 1, phase 2, and phase 3). Two tail transistors, Q7 and Q16, pull down the output terminals during phase one. The output terminal voltage of P-channel transistors Q10 and Q11 must decrease to VDD-Vth before they enter the cut-off state. Transistors Q2 and Q4 are active as long as the cross-coupled transistors Q1, Q3, Q5, and Q6 cannot turn on. Phase 2 involves the cross-coupled inverters providing strong positive feedback to raise the voltage between the output terminals. Phase 2 of the circuit transitions to phase 3 when one of the two transistors, Q14 or Q15, is disabled. Because the current through these N-channel MOSFETs is immediately terminated following the phase transition, there is no longer any static power consumption.

The dynamic comparator's transient behavior at 1 GHz is shown in Fig. 3. As can be seen, both output terminals are pulled down at the beginning of the comparison section. The strong positive feedback produced by these two cross-coupled inverters isolates the output voltages from one another because when switching from phase one to phase two, one of the output terminals through the p-channel transistor is charged [22].

B. Post Layout Simulation

Post-layout simulation has been implemented in the TSMC 65nm model in order to match the simulation results and measurement results. Figure 4 depicts the comparator's layout.

The surface area of the comparator is 10.5 µm ×17.1 µm.

The time domain analysis of the post-layout simulation is displayed in Fig. 5. The CTFET model developed in [23], which is in CTFET 20 nm technology, is upgraded (in terms of standardization and industrial comparability) to 65 nm CTFET technology to be comparable with the 65 nm CMOS technology that we shall analyze in part Ⅱ-C.

C. CTFET modelling and validation

To create the TFET model in 65 nm technology, we utilize the Ⅲ-Ⅴ model [23] which is depicted in Fig. 6.

Two capacitors, CGS, CGD, and current source (ID), are employed in the structure of the Ⅲ-Ⅴ model shown in Fig. 6 and were created using 20 nm technology. The model of Fig. 7(a, b) is initially simulated in the SILVACO ATLAS program [24] in order to move the technology from 20 nm to 65 nm.

(a)

(b)

Figure 8. Comparison of ID in proposed design with Ⅲ-Ⅴ model for (a) InAs N-TFET, (b) InAs-GaSb N-HTFET [23]

Figure 10. Diagram of CGS and CGD versus VGS of two models in 65nm and 20nm for: (a) InAs N-TFET (b) InAs-GaSb N-HTFET (c) InAs P-TFET (d) InAs-GaSb P-HTFET

For both homo/hetero structures, the Verilog-A code for the TFET transistor model in 65 nm technology is provided in [23]. Based on Fig. 9, we observe that the ID in two technologies of 20 nm and 65 nm (channel length 60 nm) is the same in both, and there is no difference between them. In Fig. 10, both models have the same CGS capacitance. In addition, when VGS is less than VDS for both technologies, the CGD capacitor for the N-channel remains the same, but the capacitance for the P-channel increases to three times that of the 20 nm technology. Yet, in VGS greater than VDS for N-channel in 65 nm technology, capacitance would grow to three times that of 20 nm technology, and for P-channel remain unchanged. In this manner, the 65 nm technology version of the proposed CTFET model was developed. The Section Ⅲ will assess the results of these comparisons.

A. MOSFET-Based Dynamic Comparator

The following parameters must be studied in order to exhibit the comparator's characteristics: 1) Power consumption (PD): This refers to the total dynamic power used by all transistors. 2) Propagation delay (tP): the amount of time, measured at 50% of the clock signal, between the edge of the clock and the end of phase one. 3) Power delay product (PDP): This term refers to the product of propagation delay (tP) and power consumption (PD). The tP is depicted in Fig. 11 versus VDD with a sampling frequency of 1 MHz and a load capacitance of 1 fF.

According to Fig. 11, as the V_DD is increased, the t_P reduces, causing more current to be pulled from it. At a sampling frequency (f_S) of 1 MHz and a load capacitance of 1 fF, Fig. 12 depicts the power consumption versus V_DD. According to the previous explanation and what is seen in Fig. 12, the power consumption rises as more current is pulled from the device.

The two curves in Figs. 11 and 12 are multiplied to get Fig. 13. The minimum and maximum amounts of PDP are shown in Fig. 13 to be 0.02 fJ and 0.0775 fJ at 1 volts and 0.5 volts, respectively. We draw the conclusion that the optimal MOSFET-based comparator design is attained at a voltage of 1V, based on Fig. 13. MOSFETs are thus not appropriate for the design of digital circuits at very low voltages, because the minimum PDP occurs at a voltage of 1V.

Figure 14. Power consumption versus sampling frequency in the MOSFET post-layout simulation of comparator in the load capacitance of 1 fF (a) V_DD = 0.5 V, (b) V_DD = 1 V.

The comparator must operate more quickly in order to raise the f_S, which leads to an increase in current and power consumption. The maximum frequencies in Fig. 14(a) and (b) are equivalent to 2 GHz and 80 MHz, respectively, with V_DD of 1 V and 0.5 V. The maximum frequency drops when the V_DD decreases, since the current consumed by it does as well. In Fig. 14(b), this problem is depicted. The comparator's reaction to high load capacitances is one of its capabilities. This circuit has a maximum capacitance of 15 pF, which is unusually high for integrated circuits.

B. Homo-Structure TFET- Based Dynamic Comparators

This section implements a homo-structure TFET-based dynamic comparator circuit. The three parameters of propagation delay, power consumption, and PDP will be investigated in comparison to the MOSFET based comparator in section Ⅲ-A.

1) Propagation delay (tP): As can be observed by comparing Figs. 11 and 16, the TFET based comparator curve has a sharper downward exponential slope than the MOSFET-based comparator, which has the same structure. CTFET technology's comparator can operate with V_DD=0.2V and deliver results that are comparable to those of MOSFET-based comparator at 1V. As a more general result, CTFET-based comparator brings the capabilities of very low voltages and very high frequency at the same time.

2) Power consumption (P_D): P_D has a second-degree relationship with VDD. Figure 17 demonstrates the correlation between P_D and VDD. When comparing Figs. 12 and 17, it becomes evident that the TFET performs proficiently with low P_D at voltages under 0.5 V, as depicted in Fig. 17. Conversely, Fig. 12 illustrates the effective operation of the MOSFET above 0.5 volts with linear P_D variations, signifying lower power consumption compared to the homo-structure TFET with its exponential changes. Consequently, for designing a comparator circuit with very low voltage and minimal power consumption, the only viable choice is the homo-structure TFET.

3) Power Delay Product (PDP): The amount of PDP is shown in terms of V_DD in Fig. 18. This figure shows that the PDP grows exponentially as the V_DD rises. As the V_DD is increased, Fig. 13 shows that the PDP of the MOSFET-based comparator drops exponentially. Consequently, we conclude that MOSFETs are ideal for the design of comparators at VDD voltages above 0.5V, particularly the V_DD of 1V, whereas homo-structured TFETs are suitable for developing comparators at a V_DD below 0.5V, i.e., very low voltage applications. The homo-structured TFETs may be employed to create very low voltage comparators.

According to Fig. 19, the power consumption rises as the sampling frequency rises, which is consistent with the equation

$$\:\:P={C}_{L}\times\:{V}_{DD}^{2}\:\times\:{f}_{s}$$

where V_DD denotes the DC power supply, f_s denotes the sampling frequency, and C_L is the load capacitance.

According to Fig. 15, the MOSFET-based comparator can support loads well up to 15 pF, and Fig. 20 illustrates that the homo-structured TFET-based comparator can support load capacitances up to 10 pF. The relation between load capacitance and power consumption is linear. MOSFET transistors were capable of supporting 1.5 times the capacitance of homo-structure TFETs because they had a higher current.

C. Hetero-Structure TFET Based Dynamic Comparators

The Verilog-A transistor model of section Ⅱ-C is utilized to create the dynamic comparator circuit in this part, based on hetero-structure TFET. The three parameters of propagation delay, power consumption, and PDP are studied in this part, as in sections Ⅲ-A and Ⅲ-B.

1) Propagation Delay (t_P): The t_P versus V_DD is depicted in Fig. 21. The propagation delay in the comparator with hetero-structure TFET has been decreased by around a tenth when compared to the homo-structure TFET, as seen by comparison between Figs. 21 and 16. Since the g_m of the hetero-structure TFET is larger than that of the homo-structure TFET, it performs better at high frequencies than the homo-structure at very low voltage applications (below 0.5 V).

2) Power consumption (P_D): In Fig. 22, power consumed is depicted versus V_DD. According to this figure, the power consumption grows by a factor of two times the square of the V_DD. By comparing Figs. 17 and 22, it can be seen that hetero-structure TFETs consume more power than homo-structure TFETs since their g_m are larger.

3) PDP: The PDP versus V_DD is shown in Fig. 23. According to this figure, the PDP value grows as the V_DD increases. As compared to Fig. 18 it can be seen that for voltages below 0.5 volts, the PDP of the hetero-structure TFET comparator is lower than the PDP of the homo-structure TFET comparator. Consequently, in very low voltage applications, the performance of the hetero-structure TFET comparator is the highest among all studied structures.

The power consumption in terms of sampling frequency is shown in Fig. 24. This graph shows that the power usage rises linearly as the sampling frequency rises.

The P_D is depicted in Fig. 25 as a function of load capacitance. This figure, together with Figs. 20 and 15, led to the conclusion that the hetero-structure TFET-based comparator has significantly larger capability to support load capacitances. Because capacitances up to 1 nF may be supported by this structure.

Table Ⅰ shows the state of the art’s implementations in 65 nm technology. The table compares simulation results for homo- and hetero-structure tunnel field-effect transistors (TFETs), post-layout MOSFET simulation data, and simulation results from other references with various specifications, such as technology node, maximum sampling frequency, load capacitance, supply voltage, power consumption, propagation delay, and power-delay product (PDP).

Device capacitances and g_m are traded off in the context of CMOS and CTFET technologies. The capacitance (C_GS and C_GD) in the transistor model of CTFET technology is significantly lower than the capacitances of comparable CMOS model. The g_m of the CMOS transistor, in contrast, is significantly greater than that of the CTFET transistor. As a result, CMOS has a lower power consumption and PDP than CTFET, while CTFET has a lower propagation delay and higher maximum sampling frequency.

TABLE I

State of the art’s implementations in 65 nm technology

Specifications	Ref. [1]	Ref. [1]	Ref. [2]	Ref. [3]	MOSFET Post-Layout Simulation	Homo-TFET	Hetero-TFET
Technology(nm)	65	65	65	65	65	65	65
Max. Sampling Frequency(GS/s)	6.66	6.66	0.125	0.125	2	3.34	25
Load Capacitance(fF)	----	----	----	----	1	1	1
Supply Voltage(v)	1	0.9	1	1	1	0.45	0.45
Power Consumption(µw)	50.57	34.3	35.5	28.2	48.66	5.16	39
Propagation Delay(ps)	47.140	47.140	87.2	446.7	89.5	97.06	11.07
PDP(fJ)	2.380	1.610	3.095	12.596	4.355	0.5	0.43

In conclusion, this paper proposes the design of a very low voltage, very low power, and very high-speed homo/hetero structure TFET-based dynamic comparator in 65nm technology and also compares these structures with the same structure in CMOS technology in post-layout simulation level. The proposed comparator structure's utilization of a dynamic latch and preamplifier allowed it to eliminate static power consumption. Moreover, the proposed comparator had a dual-rail input, which was an improvement over a 20nm structure. The post-layout simulation showed that the designed layout was reliable and robust. To provide CMOS an opportunity to compare with CTFET, a model CTFET is developed using 65nm technology. Overall, this paper present comparators that can operate at very low voltages and power, and very high speeds. The highest sampling frequency of 25 GS/s in PDP of 0.4325 fJ has been achieved in this study.

Funding: The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

Competing Interests: The authors have no relevant financial or non-financial interests to disclose.

Data availability statement: There is no data to share.

Author Contribution: All authors contributed to the study conception and design. Simulations were performed by M. Dashtbayazi. The first draft of the manuscript was written by M. Dashtbayazi and all authors commented on the manuscript. All authors read and approved the final manuscript.

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No competing interests reported.

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Analysis, Design, and Simulation of a Very Low Voltage, Very Low Power, and Very High Speed Homo/Hetero Structure TFET-Based Dynamic Comparator in 65nm Technology

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Abstract

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I. INTRODUCTION

II. STRUCTURE

III. SIMULATION RESULTS

IV. CONCLUSION

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References

Additional Declarations

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