Wireless ECG: A Sub mm-Waves, 160GHz, Vital Signs Monitoring IC, in 22nm CMOS FDSOI

doi:10.21203/rs.3.rs-4932889/v1

This paper presents a sub mm-Waves, 160 GHz Vital-Signs monitoring IC with integrated on-chip antennas. At the receiver (Rx) side, it consists of a low-noise amplifier (LNA), I/Q mixers and a variable-gain amplifier (VGA) whereas at the transmitter (Tx) side is composed of a power amplifier (PA) with I/Q voltage-controlled oscillator (VCO) and an integrated Integer-N phase-locked loop (PLL) with a 5 GHz reference signal. Realized in a 22nm CMOS FDSOI technology, the IC has a DC power consumption of 450 mW, 10 dBm transmitted saturated power (P_sat), 30 dB Rx gain with a noise figure (NF) of 8 dB. The measured phase noise of the PLL is -115 dBc/Hz @ 1 KHz and -124 dBc/Hz @ 100 KHz. The chip is followed by a FPGA that runs the detection algorithms. The chip detects the breathing rate and the heart rate of a patient positioned at 2m from an IC mounted on PCB.

Health sciences/Cardiology

Physical sciences/Energy science and technology

RADAR

sub mm-Waves

Vital Signs

Integrated Circuits

Heart Rate

Breathing Rate

A sub mm-Waves, Vital Signs Monitoring IC, with integrated antennas, shows good resolution in providing heart signals that enables ECG signals, wirelesly.
The IC was fabricated in the 22nm CMOS FDSOI technology from Global Foundry and has no high frequency wired connections with the external world. It is followed by a FPGA than runs the detection algorithms. The chip detects the breathing rate, and the heart rate of a patient positioned at 2m from the IC mounted on a PCB

Continuous monitoring of human vital signs, such as breathing rate (BR) and heart rate (HR), is essential for the early identification and even forecasting of disorders that may have an impact on a patient's wellness. There are 2 methods of sensing human vital signs, namely, the contact-based sensing and the contact-less sensing [1]. Contact-less like wireless vital signs detection utilizing radars has the particular advantage of not requiring the attachment of electrodes to the subject's body. Several radar designs have been reported in the literature for the detection and monitoring of human heart rate (HR) and breath rate (BR), including the continuous-wave (CW) radars [2], frequency-modulated continuous-wave (FMCW) radars [3]-[5], stepped-frequency continuous-wave (SFCW) radars [6] and pulse-based [7] radars. FMCW radars offer the possibility of detecting the range of the subject unlike CW, which is useful in detecting multiple subjects for surveillance. Moreover, they use relatively simpler signal processing algorithm, compared to their pulse-based radar counterparts [1]. As the HR and BR detection accuracy and the range are proportional to the center carrier frequency and the bandwidth, respectively, FMCW vital signs radars typically need to operate in the millimeter-wave frequency band to obtain good micro-doppler and range resolutions..

In this work, an I/Q VCO at 160GHz, based on differential tuning, is designed to obtain a 4.9% linear bandwidth at sub-mm-wave frequencies. Another advantage is the size of the antenna that can fit on-chip. Besides, the antenna efficiency is higher as less power is absorbed in the substrate thus, enhancing the radiated power in the air. At 160GHz, both transmit and receive antennas can be integrated on chip, eliminating critical external connections operating at 160GHz. The proposed Vital signs monitoring IC has a small footprint with the only high frequency connections to PCB running below 5GHz. By choosing the RF carrier at 160GHz the IF bandwidth can be large, providing better range resolution.

The paper is organized as follows: Section II discusses the proposed System Architecture, Section III tackles the circuit implementation, Section IV shows the measurement results and Section V draws Conclusions.

The system architecture is shown in Fig. 1. The Tx and Rx antennas are integrated on-chip and the Rx and Tx share the same Integer-N PLL with I/Q VCO. At the Rx side the Rx antenna signal is applied to the I/Q mixer. The baseband signals are obtained after demodulation by the quadrature mixer then subsequently filtered, further amplified by the variable-gain amplifier (VGA) and digitized by the ADC before being processed by a FPGA. At the Tx side the VCO is applied to a buffer and thereafter to the PA. The time domain transmitted signal, denoted by T(t) and the received signal by R(t) are:

$$\:T\left(t\right)={A}_{t}cos\left(?t+f\left(t\right)\right)$$

1

$$\:R\left(t\right)={A}_{r}cos\left[?t-\frac{4p}{?}\left({d}_{0}+f\left(t-\frac{2{d}_{0}}{c}\right)\right)\right]$$

2

where At and Ar are the amplitudes of the transmitted and received signals, respectively; ω the angular frequency of the transmitted signal; λ the carrier wavelength; c the speed of light; d0 the constant distance between the antennas and the subject; x(t) the instantaneous displacement of the chest, given by (3):

$$\:x\left(t\right)={A}_{b}cos\left({?}_{b}t+{f}_{b}\right)+{A}_{h}cos\left({?}_{h}t+{f}_{h}\right)$$

3

where A_b, A_h, ϕ_b and ϕ_h are the amplitudes and the phase shifts of the chest displacement due to breathing and heartbeat, respectively. As seen from (1) and (2), the signal sent by the radar is modulated in frequency and phase due to the displacement of the chest. This modulation is called the Doppler Effect.

For a zero-IF radar, the in-phase baseband signal B_I(t) is obtained by mixing a replica of the transmitted signal in (1) with the received signal in (2):

$$\:{B}_{I}\left(t\right)=T\left(t\right)xR\left(t\right)$$

4

Similarly, the quadrature baseband signal is obtained by mixing the received signal with a replica of the transmitted signal, shifted by a phase of 90◦:

$$\:{B}_{Q}\left(t\right)=T\left(t-\frac{p}{2?}\right)xR\left(t\right)$$

5

The above I and Q baseband signals are used in signal processing to determine the vital signs. In order to realize this architecture, on chip, we propose the following system (see Fig. 1). The two antennas for the Tx and Rx are integrated on-chip. They are bow-tie antenna with an area of 0.4mm x 0.32mm and a gain of 7dB. At the Rx side the 3-stage LNA (see Fig. 2a)) has a power gain of 17dB, a NF less than 8dB. and the input reflection coefficient of S₁₁<-12dB. At the Tx side (see Fig. 2c)), the three stage PA has a power gain of maximum 10dB and OP_1dB compression of -4.2dBm and a saturated power of 10dBm. The Integer-N PLL employs feedback dividing ratio of 256. The first and the second divider are injection locked dividers from 160GHz to 80GHz and 80GHz to 40GHz (Fig. 2d)).

The following dividers are classical CML dividers (see Fig. 3a)). The 5GHz external reference is divided by 8 and used as internal reference for the PFD. LFMCW modulation at RF is achieved by injecting a sawtooth signal at the input of the VCO (see Fig. 1), generated internally from an external rectangular signal provided by a FPGA. The VCO has an output frequency of 159.5GHz to 167.5GHz and a measured phase noise of -136dBc/Hz @ 1MHz. I and Q baseband signals are applied to the FPGA (ADS9-V2EBZ). Firstly, those signals are digitized. The ADCs are AD9081 4GSPS, 12-bit RF ADC. After digitization of the I and Q baseband signals we generate the phase signal and after FFT we get respiration rate and heart rate. More details in Methods.

The stages of the LNA in Fig. 2a), are common-source stages at the input and the output whereas they are cascoded stages in between. For all stages we employ transmission lines (TL) for their reliable model and compactness at those frequencies.

For the first stage we did not use a cascode stage as the cascode stage will introduce extra noise at higher frequencies and is important that the first stage has the lowest noise possible. Stages 2,3,4,5,6 and 7 are implemented as cascode stages to minimize S12 of the LNA and improve the reverse isolation. The noise of those stages is of lesser importance as the first stage gain will render the noise introduced insignificant. Regarding matching network at the input of the LNA and PA, the RF input is applied to a 50 Ohms transmission line TL1 that brings the signal to the amplifying stages. Capacitor C1 acts as a DC blocking capacitor as the shunt transmission line TL2 is connected to ground. The role of TL2 is to bring the input impedance seen at the gate of transistor M1 of the first stage to 50 Ohms for matching purposes. The capacitor C2 is a DC blocking capacitor for the bias V_BIAS at the gate of M1. The voltage V_BIAS is generated from a diode connected transistor biased externally from a constant current source. By this, the design is less sensitive to V_T mismatch as the current in the stages are constant. Each stage uses a T-line as load that resonates with the capacitance seen at the input of next stage at the desired frequency. There is no inter-stage matching as the PA stages are not realized in a discrete form and the stages are very close to each other. The design criteria for this are to maximize the voltage at the gate of the next stage.

c) Measurement Setup PA

At the output, the output impedance of the transistor, the load transmission line and the series capacitor will provide a 50 Ohms impedance for matching with the output measurement equipment. All stages of the PA shown in Fig. 2c), are common-source stages. Figure 2b) shows the schematic diagram of I/Q VCO. It consists of two identical cross-coupled pairs M1, M2 and M3, M4 with transmission lines load. The two stages are coupled each other with M6, M7 and M8, M9. For connecting the VCO to the I/Q mixers the VCO outputs are amplified with M9, M10 and M11, M12. By altering the current flowing in the cross coupled pairs and the current flowing in the coupling stages in a differential way, we can linearly change the oscillation frequency. The differential charge-pump control voltages VCTRL + and VCTRL- are applied to the resistors R1 and R2. The tuning differential voltage is transformed in a differential current using M13, M14 and M16, M17. In Fig. 2d) the VCO outputs are applied to a buffer that drives the PMOS transistor M5 of the frequency divider. The current of M5 injects the VCO signal in the middle point of the TL3 and TL4 transmission lines as load of the cross-coupled pair M1, M2.

The output of the divider is thereafter amplified by M3, M4. The output of the first injection locked frequency divider is applied to a second injection lock divider operating at 40GHz.

The output of the chain of frequency divider is applied at the $\:DIV$ and $\:\stackrel{-}{DIV}$ inputs and the 5GHz Reference at $\:REF\:$and $\:\stackrel{-}{REF}$ inputs of the PFD. The PFD outputs are applied to a differential Charge Pump shown in Fig. 3b). The transistors M₁-M₄ are driven differentially by UP and DOWN signals from PFD. Therefore, the two I₀ current sources from GND and VDD will be steered in transistors M₁-M₄ and the differential Loop Filter (LF) based on R₁, C₁ and R₂, C₂. The resistors R₂ connected to V_CM will set the common-mode voltage at the outputs of CP to V_CM.

The chip, shown in Fig. 4a), was realized in the 22nm CMOS FDSOI process from GF and has an area size of 1.25 mm x 1.25 mm. The integrated bowtie antennas have inter-layers of metal fills for metal density DRC rules.

This doesn’t affect the 7dB gain of the antennas and their efficiency. The LNA was measured on a separate breakout (see Fig. 4b)) and the results are shown in Fig. 5a). The 3-stage LNA has a power gain of 17dB, a NF less than 8dB and the input reflection coefficient of S₁₁<-12dB. The 3-stage PA measured on a separate breakout (see Fig. 4c)) has input reflection coefficient of S₁₁<-10dB in abroad range and a power gain of 10dB (Fig. 5c)), a maximum saturated power of 10dBm and OP1dB of 7dBm (see Fig. 5d). Figure 5b) shows the phase noise of the PLL and the output spectrum of the PLL (inset). The measured phase noise of the PLL is -115dBc/Hz @ 1 KHz and − 124dBc/Hz @ 100 KHz. This was measured on a PLL breakout. Figure 5e) presents the tuning curve of the VCO versus the differential control voltage V_CTRL. It features a classical S curve with a range of 159.5GHz to 168.5GHz. Figure 5f) presents the measured synchronization range of the frequency divider and shows the linear proportionality with injected signal. Due to the limitation of the tuning range of the VCO, the last measured point (in blue) at -20dBm input power is extrapolated from the previous

TABLE I

Performance Summary and Benchmark

REF	Tech.	Arch.	Freq. [GHz]	Tx Pout [dBm]	Pn@100KHz [dBc/Hz]	Ref. Freq.	Rx G [dB]	Rx NF	Pdc [mW]
[4]	22nm FDSOI	2Tx, 2Rx, PLL	151–160	2	-90	11.1 MHz	15	10	1130
[14]	22nm FDSOI	Tx, Rx	123–146	2.8	-	-	27	8	394
[16]	28nm CMOS	Tx, Rx	127–154	11.5	-	-	80	8.5	500
[15]	SiGe BiCMOS	Tx, Rx	135–170	13	-	-	65	8–11	2350
[17]	SiGe:C HBT	Tx, Rx	155–165	1	-	-	-	12	749
[18]	SiGe BiCMOS	1Tx, 2Rx PLL	145–168	-4	-68	600 MHz	27	19.3	1800
[3]	0.13u SiGe	FMCW	240	5	-70	1GHz	10	21	1800
[19]	65nm CMOS	FMCW	160	4	-	-	42.5	22.5	2200

measurement point. This was measured on a divider breakout. The IC is followed by a FPGA that processes the I/Q baseband signals and run the detection algorithms for breathing/heart rate. In Fig. 6a) the I/Q signals and constellation before and after phase and amplitude mismatch corrections. In Fig. 6b) we presented the breathing rate and heart rate. The heart rate shows ECG quality signal.

We presented a 160 GHz Vital Signs monitoring IC with integrated antennas. It consists of a LNA, I/Q mixers, VGA and a PA with I/Q VCO shared by the Rx and Tx and integrated Integer-N PLL with a 5GHz reference. Realized in a 22nm CMOS FDSOI technology from GF, the IC has a DC power consumption of 450mW, 5dBm transmit power (without the 7dB antenna gain) 17dB Rx gain with a NF of 8dB. The measured phase noise of the PLL is -103dBc/Hz @ 1 KHz and − 128dBc/Hz @ 100KHz. The chip detects the breathing rate and the heart rate of a patient positioned at 2m from the IC mounted on a PCB. The heart rate shows an ECG quality signal that could open new avenues for a wireless ECG.

In order to detect the breathing rate and heart rate we are using an FPGA (ADS9-V2EBZ) for implementing the algorithms. In a homodyne receiver, as in our case, offset will imbalance the I and Q signals at baseband. The I-Q signal balancing is performed using the S.W. Ellingson algorithm [11]. S.W. Ellingson is a straightforward algorithm that corrects both the

amplitude and phase imbalance of I-Q signals (see Fig. 6a)). After I-Q imbalance correction, the phase of the range bin where the target is detected is found. The range resolution of the radar deployed is 4 cm which is much larger than the displacement of the chest which is generally assumed to be between 1mm to 12 mm. Therefore, no bin migration occurs, and the range bin of interest is a column vector. The classic algorithm to demodulate the phase of the selected range bin is the arctangent algorithm. However, due to domain restriction within $\:[-\frac{p}{2},\frac{p}{2}]$ and the possibility of noise induction during phase unwrapping, another more efficient algorithm, called modified differential and cross-multiplication (DACM) algorithm is used. A detailed description of the algorithms used are presented in [11]. The results are presented in Fig. 6, where the measured breathing rate and heart rate are shown. The heart rate shows an ECG quality signal that could open new avenues for a wireless ECG. Table 1 shows the performance summary and benchmark. Compared with other designs from literature this design has the second lowest power consumption ([14] has a lower Tx Power of 2.8dBm), the lowest phase noise and lowest NF for the receiver (together with [14] and [15]).

Data sets

The datasets generated and/or analyzed during the current study are not publicly available due to patenting of the circuit and specific requirements from our partners but are available from the corresponding author on reasonable request.

Competing interests

The authors declare no competing interests.

Author Contribution

M.S lead the electrical characterization with help from M.G. M.S contributed to technical analysis of the results. Manuscript writing was led by MS and M.G. Both authors discussed the results and commented on the manuscript.

Data Availability

The datasets generated and/or analyzed during the current study are not publicly available due to patenting of the circuit and specific requirements from our partners but are available from the corresponding author on reasonable request.

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No competing interests reported.

Wireless ECG: A Sub mm-Waves, 160GHz, Vital Signs Monitoring IC, in 22nm CMOS FDSOI

Status:

Version 1

Abstract

Figures

Highlights

1 Introduction

2 System Architecture

3 Circuit Design

4 Measurement results

5 Conclusions

Methods

Declarations