A New Step Up Nine Level Switched Capacitor Multilevel Inverter

doi:10.21203/rs.3.rs-5004743/v1

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A New Step Up Nine Level Switched Capacitor Multilevel Inverter

https://doi.org/10.21203/rs.3.rs-5004743/v1

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In response to rising expectations for more efficient and better power generation, the switched-capacitor multilevel inverter (SCMLI) was developed. Most recently, SCMLIs were created to allow for step-up ac output via inversion and single-stage voltage boosting. This study presents a boost type single source nine-level (9-level) SCMLI that uses two capacitors and one diode in an effort to reduce the number of components. The capacitor's voltage boost from a single source is achieved through the series-parallel connecting procedure. No more than twice the input voltage can be applied to the semiconductor devices under any given condition. In order to raise the voltage levels without adding more dc input, the suggested SCMLI can be expanded with a minimal number of components. After a thorough evaluation of the power losses and circuit performance, the design is confirmed to be superior by comparing it to newly designed single-phase 9-level MLIs. In order to confirm the key characteristics of the 9-level SCMLI in dynamic operational settings, we offer comprehensive simulation and experimental findings.

Boost inverter

reduced components

self-voltage balance

Single-source

switched-capacitor

Switching loss

Owing to the increase in clean power generation demand, varieties of power converters have been investigated for efficient power conversion. Multilevel inverters (MLIs) are one among these converters, which play a key role in producing high-quality AC output from the dc input. By utilizing a combination of direct current sources, switches, diodes, and capacitors, MLIs are able to create an output that resembles a sinusoidal wave. The output of an MLI has low distortion and therefore, can improve the power quality while keeping the size of the filter low [1]. Things are shifting in the energy sector right now. The ecosystem suffers permanent harm as a result of the production of electrical energy from unstable or fossil fuel sources. Clean energy sources, such as solar and wind power, are being promoted by governments as a solution to this problem. To link these renewable energy sources to the grid and individual appliances, many families of power converters have been developed. Interchangeable multilayer inverters (MLIs) are crucial for converting DC to AC sources [2]. In addition to producing high-quality, efficient power, MLIs have far lower levels of harmonics, electromagnetic interference, voltage stress, etc., when compared to two-level inverters. Key advantages of MLIs, including as modularity, fault tolerance, dependability, minimal power loss, etc., have made them popular in the research community at the moment [3].

Traditional multilevel topologies come in three flavors: the neutral-point-clamped (NPC), flying capacitor (FC), and cascaded H-bridge varieties. Nevertheless, AC voltage conversion is necessary since most electric energy generated by renewable sources, including fuel cells and solar arrays, is of low voltage [4]. A common method involves using a normal multi-level interconnect (MLI) at the back end and a DC-DC boost converter at the front end [5]. Keeping the voltage balance of the capacitors in NPC and FC topologies requires complex control algorithms, current and voltage sensors, or additional balance circuits. More complexity and less efficiency are the results of all of them. The active switches, power diodes, and DC sources that make up these converters allow them to generate a staircase voltage waveform with minimal THD. In general, power semiconductors in MLIs are not as voltage-tolerant as their more conventional two-level equivalents [6]. The article "A Switched-Capacitor Multilevel Inverter Using Series-Parallel Conversion With Reduced Components" suggests a fresh method for creating a multilevel inverter. The multilayer voltage output achieved by using a switched-capacitor architecture with series-parallel conversion is the main innovation. Notable in comparison to conventional multilevel inverters is this design's capacity to decrease the amount of components. Voltage management and balancing are made easier with the switched-capacitor setup. The inverter is able to provide various voltage levels with a minimum of components thanks to series-parallel conversion. This helps to save costs and enhance dependability while also simplifying the design overall. The suggested inverter's theoretical foundation, operational principles, and benefits over traditional multilevel inverters are probably covered in the paper. Potential advantages that may result from reducing the number of components include simplified systems, increased efficiency, and maybe less maintenance needs[7].

Due to the increasing control complexity and the large number of semiconductor devices needed for higher levels of output voltage, the size and cost remain the primary concerns, despite these many advantages[8]. Despite these benefits, multilevel inverters' complexity in structure and control mechanism is their biggest downside. An rise in NPC voltage, for instance, would necessitate more clamping diodes and capacitors, which in turn would increase the converter's size and loss. Also, in increasingly advanced NPC topologies that call for intricate control strategies, achieving dc-link capacitor voltage balancing becomes an insurmountable obstacle[9]. Another issue is that SC-CMIs don't operate uniformly, which is a feature that cascaded multilevel inverters rely on[10]. Some problems with NPC arise as the number of levels increases, such as the issue of voltage unbalancing of dc-link capacitors and the high number of semiconductors that are needed. These characteristics restrict its use in commercial settings.[11]. The main drawbacks of MLIs are their complexity regarding the structure and control technique[12].

The main challenge with multilayer inverters is to stabilize the voltages of more capacitors with voltage balancing techniques while decreasing the number of individual DC sources. Because of this, the price of multilayer inverters can go down and their usage can go up [13]. Designed to reduce the amount of components required for voltage balancing, SC MLI structures use a single DC source, a limited number of capacitors, and semiconductor devices to increase voltage levels. These structures eliminate the need for inductors, transformers, and a separate circuit. The recently disclosed MLI in [8] requires multiple sources. The revealed topologies generate two times the voltage boost output by employing the series-parallel voltage balancing method. There is a fourfold increase in boosting gain with a comparable increase in switch count in MLIs created. While MLI uses fewer switches, it makes more use of capacitors and diodes, as described in [14].

This work presents a SolarCell MLI that is compatible with PV systems and has nine levels and eight switches. The article is divided into the following six sections. Section II analyses the SCMLI's detailed working principle, and Section III compares it to the well-known 9-level MLI topologies. A high-level summary of the proposed MLI's control mechanisms is given in Section IV. In Section V, we detail the SCMLI simulation analysis, and in Section VI, we present the experimental results obtained from several dynamic test situations. Section VII provides more discussion, while Section VIII offers final observations.

A. Circuit Description

You can see the proposed SCMLI in Fig. 1(a). Eight switches, a diode, and two capacitors make up the SCMLI. With only one photovoltaic (PV) source, you may charge the capacitors and create an output with nine levels. It is easier to achieve maximum power tracking, DC-link balancing, and MLI control in standalone/grid-tied PV systems with the proposed SCMLI rather than with a multi-dc ML, which requires individual module control [15]. Since the suggested MLI only requires one dc source at the input, it eliminates the need for a second dc-dc boost stage when used to PV systems. To correspond with the needed grid voltage, four identical PV panels are required in a traditional single-stage, 9-level symmetrical CHB MLI. Alternatively, the suggested MLI's inherent boosting ability allows it to achieve the needed output with just a single PV panel of the same rating. Charging the SCs does not necessitate an external balancing circuit. Using a series-parallel charging and discharging approach, capacitors C1 and C2 are self-balanced at Vdc and 0.5Vdc, respectively. In the output voltage steps of 0, ± 0.5Vdc, ±Vdc, and + 1.5Vdc, capacitor C1 is charged, and capacitor C2 is charged during the steps of -0.5Vdc and − 1.5Vdc. In particular, the total time it takes to charge and discharge the capacitors is less than a fundamental cycle, and the discharge is symmetrical on the positive and negative halves of the cycle. The capacitor voltages will recover quickly because of this. Figure 1(c) shows the SCMLI's operating principle in detail. As C2 discharges, the first voltage level (0.5Vdc) is generated with its support. At the same time, C1 is charged to Vdc through switch S2. By means of switch S2, the first voltage step (1Vdc) is applied to capacitor C1. During each voltage step, the capacitor C1 is periodically charged by switch S2 and discharged through switch S1 in the opposite direction. During the 1.5Vdc synthesis, capacitor C2 discharges, and the 2Vdc output is the result of adding the voltages from capacitor C1 and the input source. By disabling S3 and S4, a comparable method is employed to produce the negative voltage steps. Furthermore, the suggested SCMLI is capable of adequate operation under both high and low power factor loads.

B. Control Strategy

A multilevel converter employs a particular modulation strategy to apply gate pulses to the switches. In order to generate output voltage levels while minimizing the impact of harmonics, the modulation strategy is crucial. High-frequency modulation schemes include carrier-based PWM and space vector modulation, whereas the fundamental frequency method, selective harmonic elimination (SHE), is used in low-frequency schemes [15]. Phase disposition multicarrier pulse width modulation (PDPWM) is used to modulate the suggested topology. Researchers discovered that PDPWM, a modulation method, is easy to implement and results in less harmonic distortion [11]. The pulse width modulation (PDPWM) method compares two carrier waves, one with the same amplitude and frequency of switching, to one with a 50 Hz reference sine wave. The acquired pulses are utilized to activate the switches at a specific voltage level. Here, the control method can be extended to higher voltage levels; the nine-level inverter is described in Fig. 2 and its explanation follows. No level by comparing (Nlevel − 1) carrier signals, a number of output voltage levels can be generated [16]. In this case, a reference wave (Vref) and eight carrier signals (Vc1–Vc8) are needed for a nine-level output voltage. Table 1 shows the switching pattern that is determined by comparing the carrier wave with the reference wave.

Table 1

Switching Sequence of Proposed Topology
Switching Sequence								Voltage output
S₁	S₂	S₃	S₄	S₅	S₆	S₇	S₈	Voltage output
1	0	1	1	0	0	0	1	2V_dc
0	1	1	1	0	0	1	0	1.5V_dc
0	1	1	1	0	0	0	1	1V_dc
0	1	0	1	0	1	1	0	0.5V_dc
0	1	0	1	0	1	0	1	0V_dc
0	1	0	0	1	1	1	0	-0.5V_dc
0	1	0	0	1	1	0	1	-1V_dc
1	0	0	0	1	1	1	0	-1.5V_dc
1	0	0	0	1	1	0	1	-2V_dc

The design of the filter inductor and the capacitors is described in detail in this section. Additionally, all stressors related to device voltage and current have been thoroughly examined. We have covered the ins and outs of thermal modeling as well as loss analysis for the diodes and switches. The capacitor's design limits the maximum voltage ripple to 10% of its rated value [4].

A. DETERMINATION OF CAPACITOR FOR THE PROPOSED SCMLI.

The capacitance value of the proposed inverter is engineered to provide various voltage levels I output while maintaining an acceptable ripple. The boosted voltage steps in positive and negative cycles are controlled by capacitors C1 and C2, whose capacitance value is mainly influenced by two factors: 1) the time it takes to charge or discharge, and 2) the maximum permissible voltage ripple across them.

1) C₁ design

The ripple on capacitor C1 is greatest in zones I and VIII. Reason for the highest level of ripple in zone IV. In zone IV, the highest ripple occurs because capacitor C1 charges capacitor C2 to 0.5Vdc using its maximum energy. Zone I should not be used to drain energy from capacitor C1, as zone IV has already charged capacitor C2. Therefore, just the Longest Discharge cycle (LDC) in zone V is used to determine C1.

The following is the voltage ripple of capacitor C1:-

$$\:\varDelta\:{V}_{c1}=\:\frac{1}{{C}_{1}}{\int\:}_{0}^{\raisebox{1ex}{$\theta\:1$}\!\left/\:\!\raisebox{-1ex}{${\omega\:}_{0}$}\right.}{i}_{c1}\left(t\right)dt$$

C₁ $\:\ge\:\frac{{I}_{c1avg}\:x\:\left(\theta\:1\right)}{\varDelta\:{V}_{c1}\left(\omega\:0\right)}$ (2)

Where, $\:{\theta\:}_{1}={\text{sin}}^{-1}\frac{{A}_{c}}{{A}_{m}}$

The lowest value of capacitor C₁, which is 4000µF, may be obtained from Eq. (2) by plugging in I_C1 and the average value from the Simulink results. This was done for ∆V_c1 = 5V. However, in both modeling and experiment, voltage steps have been produced with the enhanced value of 4700 µF. As illustrated in Fig. 3, the voltage ripple that has been measured is 4.1V and 6V, respectively.

2) C₂ design

Maximum discharge of capacitor C2¬ occurs in zone IV. 10% is the foundation value for voltage ripple ∆V_c2 in the design of C2.

For zone IV from Fig. 3,

$$\:\varDelta\:{V}_{c2}=\:\frac{1}{{C}_{2}}{\int\:}_{\raisebox{1ex}{${\theta\:}_{2}$}\!\left/\:\!\raisebox{-1ex}{${\omega\:}_{0}$}\right.}^{\raisebox{1ex}{$\theta\:3$}\!\left/\:\!\raisebox{-1ex}{${\omega\:}_{0}$}\right.}{i}_{c2}\left(t\right)dt$$

C₂ $\:\ge\:\frac{{I}_{c2avg}\:x\:(\theta\:3-\theta\:2)}{\varDelta\:{V}_{c2}\left(\omega\:0\right)}$ (4)

Where $\:{\theta\:}_{2}={\text{sin}}^{-1}\frac{2{A}_{c}}{{A}_{m}}\:and\:{\theta\:}_{3}={\text{sin}}^{-1}\frac{3{A}_{c}}{{A}_{m}}\:$

By plugging in IC2 and the average value from the Simulink findings, we can find the lowest value of C2 from (4), which is 4000 µF, given that ∆V_c2 = 10V. The experiment and simulation utilized the greater value of 4700 µF to generate the voltage steps. Additional evidence of a 9.3V and 10V voltage ripple can be found in Fig. 3.

B. Total Standing Voltage Calculation.

If you want to know how efficient and cost-effective MLI converters are, you need to know the total standing voltage (TSV). Switches with lower ratings and less stress across them might make inverters more cost-effective. It is TSV's job to grade and categorize semiconductor electronics. Among them are diodes and integrated gate bipolar transistors (IGBTs). The standing voltage is the highest potential applied voltage across an off-state semiconductor switch. The MSVs of all the switches are added together to get the total standing voltage (TSV). It is possible to get a ballpark estimate of the total standing voltage by using the current switch states. If the output voltage law is unaffected by the MSV of this particular loop, we can declare switch S1 to be off. Consequently, the above configuration shows the maximum standing voltage across each semiconductor switch.

MVS₁ = MVS₂ = V_dc (5)

MVS₃ = MVS₄ = MVS₅ = MVS₆ = 2V_dc (6)

MVS₇ = MVS₈ = V_dc / 2 (7)

According to the suggested inverter structure, the inverter's total standing voltage is equal to the maximum standing voltage across all of the switches. As a result, the TSV value corresponds to the standard nine-level topology.

TSV_{proposed module} = $\:\sum\:_{i=1}^{8}{MVS}_{i}$ = 11V_dc, (8)

The following is the proposed MLI's total standing voltage (TSV) as a percentage of the maximum output voltage (TSVp.u):

TSVp.u = $\:\frac{TSV}{{V}_{0},\:max}$ (9)

Where TSVp.u is 5.5.

As a percentage, the voltage stress distribution across each switch can be determined by dividing the total converter standing voltage by the maximum static voltage (MSV) across all of the switches. At 2Vdc, the greatest voltage stress that switches S7 and S8 undergo representing 25% of the entire voltage stress—is 50%. While all six switches were subjected to the full voltage stress, switches S1, S2, S3, S4, and S6 were only subjected to half of it. Figure 3 shows the prevalence of voltage stress as well as the percentage of stress that each switch has encountered. Because they share the voltage stress effectively, the inverter is able to use more switches and low-TSV dc sources.

There is a distinct distribution of the total supply voltage (TSV) across the inverter switches. There is a 100% voltage stress on half of the inverter's switches. Concurrently, topologies grow in size and cost due to the requirement for high-rated switches and the fact that 25% of switches undergo minimum voltage stress [15]. The inverter is both simple and inexpensive because it uses switches with varying ratings.

C. COST FUNCTION

In order to determine the appropriate applicable MLI, several factors are considered when calculating the cost function (CF). These factors include the total standing voltage (TSV), the number of switches (Ns), the driver (NGd), the capacitor (Nc), the main and auxiliary diodes (ND and NAD), and the number of switches. The following is the formula for calculating the CF of an inverter:

CF = (Ns + N_Gd + N_Dc + Nc + β*TSV) (10)

The total standing voltage is given more weight than the component count when β is used as the weighting factor. The inverter's structural qualities are improved by a low value of CF. The CF per level is the metric that is utilized for comparison. Accordingly, the cost function is computed at β = 0.5 and 1.5.

CF (β = 0.5) = 25.5, CF/level = 2.83 (11)

CF (β = 1.5) = 36.5, CF/level = 4.05 (12)

D. Loss Analysis

When adding together the power losses in all of the semiconductor devices in the dc-ac converter, we get the total loss[16]. The suggested inverter experiences power loss due to switching and conduction losses.

i) Switching Loss

Whenever a switch goes from being on to off, or back again, it loses some of its power. For a given switch, the overlapping waveforms of current and voltage are considered during the changeover. One way to calculate the overall switching loss of all n system modules is to

Psw,_N = $\:\frac{1}{2}\sum\:_{N=1}^{4N+6}\left[{V}_{0}{I}_{0}\right({t}_{on}+{t}_{off}\left){f}_{sw}\right]$ (13)

The voltage stress across the semiconductor switch (V0), the current flowing through it (I0), and the timings ton and toff, which represent the on and off states of the switch, are equal. Here, fsw is the switching frequency.

ii) Conduction Loss

For one-way operation, the proposed design makes use of switches that are integrated gate bipolar transistors (IGBTs) with antiparallel diodes. In an MLI switch, the total loss of conduction power is the sum of the losses of the integrated gate bipolar transistor (IGBT) and the diode. It is possible to determine the IGBT and diode's conduction loss via

P_{on, IGBT} = V_{on, IGBT} I(t) + R_IGBT I^α+1(t), (14)

P_{on, Diode} = V_{on, Diode} I(t) + R_Diode I²(t) (15)

In the conduction period (on state), the voltage across the IGBT is denoted as Von, IGBT, while the voltage across the diode is denoted as Von, Diode. The characteristic of an IGBT, where A is a constant, defines the sinusoidal current I(t) that flows through a switch with a maximum current of Im. Just so we're clear, (Non, IGBT) represents the number of IGBTs and (Non, diode) represents the number of diodes. Accordingly, the suggested topology's average conduction power loss (Pc,avg) is

P_{c, avg} = $\:\frac{1}{\pi\:}\int\:{(N}_{on,IGBT}{P}_{on,IGBT})+\left({N}_{on,diode}{P}_{on,diode}\right)dwt$ (16)

All of the module failures By adding the two losses from equations 13 and 16, we get the total losses, or p_losses.

P_losses = P_sw + Pc, avg. (17)

The process of determining switch loss using the PLECS program is illustrated in Fig. 4. Calculation of the losses in the proposed module is done in the PLECS-based simulation model. A switch thermal module characteristic (IKY50N120CH3) is used to conduct the analysis. A good approximation of the suggested module converters' efficient distribution has been derived using datasheets supplied by power semiconductor manufacturers. The suggested module's power loss study is conducted on an input power of 1 kW with an RL load. Figure 4 shows the distribution of losses and the consequence of each switch's particular loss.

(A) (B)

Figure 5 (A) Dispersion of Losses Among Switches (B) Total loss of inverter.

An efficiency of 97.6% is achieved with power semiconductor switches, with a total loss of 23.5W for a resistive inductive load. The distribution of the inverter's total conduction and switching losses is shown in Fig. 5(B). We find that switching losses account for only 6% of total losses, which is significantly lower than conduction losses, which account for 94% of inverter losses.

To appraise the dominance of the proposed 9-level SCMLI, a thorough comparison is carried out with recent-art 9-level (N_l) MLIs. The comparison in Table 1 includes different parameters such as number of switches (N_sw), number of capacitors (N_cap), number of diodes, number of gate driver circuits, maximum voltage stress(MVS), TVS, Gain, and THD.

Most of the recently developed structures require a single input source, unlike the symmetrical topologies and asymmetrical structures. From the high voltage gain with minimum TSV point of view, the SCMLI in [17] has a comparatively smaller number of switches and drivers. The circuit, though, needs additional capacitors and diodes. Voltage gain can't be more than double the input voltage, and four of the circuit's switches are rated at maximum voltage stress. In the suggested circuit, like in most other topologies, the load current path never contains more than half of the total number of switches. Moreover, the ability of the proposed SCMLI to change the polarity without a full bridge at the back end guarantees low MVS while possessing high voltage gain. On the other hand, the 9-level topologies in [17] and [18] lack the ability to boost the voltage.

Table 1

COMPARISON OF THE SINGLE SOURCE SWITCHED CAPACITOR BASED NINE-LEVEL MLIS
Parameters	[2]	[17]	[18]	[19]	[20]	[21]	[22]	[23]	Proposed MLI
N_sw	8	7	12	8	11	8	10	12	8
N_d	4	4	0	2	0	2	2	0	1
N_c	4	2	3	4	2	2	2	2	2
N_gd	8	7	11	8	10	8	9	12	8
TSV_p.u	4	4.25	6	NA	10	4.36	4.5	5.25	5.5
MSV_(vdc)	4	1	4	NA	2	2	1	2	2
Gain	4	1	4	1	2	2	2	4	2
THD%	11.8	15.33	17	18.36	NA	NA	NA	NA	2.5

A laboratory-scale prototype and simulations in the MATLAB/Simulink environment were used to test the operability of the proposed 9-level SCMLI. Table II provides the details of the testing apparatus.

A. SIMULATION RESULT

The Switching pulses are obtained using a fundamental frequency switching scheme [8],[9], [14]. Using the Fourier series, the 9-level staircase output waveform can be expressed mathematically as:

Table 2

Simulation and Experimental Test Parameter
Parameter	Values
Input dc source (Vin)	100V
Capacitor (C₁ and C₂)	4700µF
Nominal output frequency (f_n)	50Hz
Load 1 (R-Load)	100Ω
Load 2 (RL-Load)	100Ω-200mH.
Load 3 (RL-Load)	200Ω-400mH.

First, the proposed circuit is connected to load 1 and the result is obtained. Under selected M values under pure resistive load, the load current pattern is identical to 9- level load voltage waveform as shown in Fig. 6. The fundamental value is maintained even at low M (0.5). The capacitor voltage is maintained at 100v (Vin) and 200v (Vout) without using any auxiliary voltage balancing control. The harmonics analysis of the Vout in Fig. 6(b) depicts the total harmonic distortion decrease as M increases. The targeted harmonics are negligible at high M (1).

The operation of the proposed circuit is also verified under dynamic varying inductive loading Fig. 7. The load voltage waveform is undistorted and the load current pattern is clean sinusoidal. The capacitor voltage is retained at the desired value under sudden load transient that assists in the synthesis of 9- level, 2 times boost output (200V). Further, under sudden variation in the input DC voltage, Fig. 8 depicts the capacitor voltage are gradually changes and inherently settling as desired.

B. EXPERIMENTAL RESULTS

The real-time performance of the 9-level SCMLI is further verified using a real-time OPAL-RT 4510 simulator as shown in Fig. 9. The system parameters are mentioned in Table II. the test bench includes a PC and OPAL-RT 4510 controller. Results are captured on a DSO7104A oscilloscope.

Both the steady state and transient performance of the system is tested under different load conditions. Figure 10 and Fig. 11. shows the steady-state load voltage corresponding load current waveform under load 1(unity PF). The steady-state capacitor voltage (VC1 and VC2) are about 100V and 50V, which produces a twice boost 9-level output. Under sudden switching of loads from no-load to load 2 (0.8 PF), Fig. 11 shows the load current straight away increase without any distortion in the load voltage. Keeping with the results of the simulation, the RMS value of the load voltage is affected by dynamically varying inductive loading. Figure 11 shows a smooth transition from 1.7A to 1.5A for the RMS value of the load current under dynamic changing inductive loading, which is consistent with the simulation findings. In addition, at the same time maintains the desired 9-level output. The capacitor's voltage is inherently settled without any auxiliary controller. While maintaining the desired 9-level twice boost output. The voltage THD and switching power losses are very low due to fundamental switching operations. Whereas, the current THD is low due to the sinusoidal –like current waveform under the inductive loading.

The research presented here introduces a 9-level boost-type SCMLI with two SCs and a decreased component count. To keep a steady-state voltage across the SCs of Vin and 0.5Vin, they are charged in parallel and discharged in series. Therefore, the proposed MLI is devoid of any auxiliary voltage balancing circuit and in turn, reduces the control complexity. Further, the AC output is synthesized without using a conventional full-bridge that resulting in significant voltage stress reduction and the MVS is limited to 2Vin. No matter how long the circuit is, the MVS and the quantity of dc sources stay the same. With these distinctive features, the proposed SCMLI is highly suitable in single-stage PV systems. The operational principles, charging-discharging process, and power loss analysis have been discussed in detail. A thorough comparative analysis reveals that the proposed SCMLI achieves a remarkable reduction in cost factor while retaining the other advantages. The suggested 9-level SCMLI is feasible under dynamic working conditions, according to both the simulation and experimental study.

Author Contribution

Sharvendra kumar omre: Conceptualization, Designing the Topology, Parameter Calculations, Methodology, Comparative study, Validation, Investigation, Writing-original draft preparation.Ritula Thakur: conceptualization, validation, results analysis, investigation, writing-review and editing, supervision.Kaibalya Prasad Panda: conceptualization, Validation, Results analysis, Investigation, Writing-review and editing, Supervision.All authors contributed significantly to the work’s idea and design, as well as the acquisition and analysis. The final version to be published was approved by all authors.

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A New Step Up Nine Level Switched Capacitor Multilevel Inverter

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Abstract

Figures

I. INTRODUCTION

II.PROPOSED 9-LEVEL INVERTER

III.PASSIVE COMPONENTS DESIGN, TSV CALCULATIONS, AND LOSSES

IV. COMPARATIVE ANALYSIS WITH PROPOSED SCMLI

V. RESULTS

VI. CONCLUSION

Declarations

Author Contribution

References

Additional Declarations

Status:

Version 1