Residue-free wafer-scale direct imprinting of two-dimensional materials

doi:10.21203/rs.3.rs-5042296/v1

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Residue-free wafer-scale direct imprinting of two-dimensional materials

https://doi.org/10.21203/rs.3.rs-5042296/v1

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Two-dimensional (2D) semiconductors hold great potential for next-generation electronics in extending Moore’s law beyond silicon. However, despite pioneering advances in proof-of-concept device demonstration and wafer-scale crystal synthesis, its industrialization will be hampered by the lack of a compatible residue-free patterning technology. To overcome this limitation, we demonstrate a facile metal-stamp imprinting method for patterning 2D film into wafer-scale arrays of intrinsic quality. The three-dimensional (3D) morphology of metal-stamp forms a local contact at stamp-2D interface, ensuring that the 2D material could be selectively exfoliated and leaving 2D arrays on grown substrate. Furthermore, detailed microscopy and spectroscopy characterizations are conducted to confirm their clean surface and undamaged crystal structure. A statistical analysis of the 100 back-gated transistors and 500 top-gated logic circuits shows a marked improvement in device uniformity (20 times lower variation of threshold voltage) than traditional method, and a high device yield of 97.6% on 2-inch wafer. This work achieves a residue-free, time-saving, and widely applicable patterning technique for 2D materials and lays the foundation for the future integration of 2D electronics in industry.

Physical sciences/Nanoscience and technology/Nanoscale devices/Electronic devices

Physical sciences/Nanoscience and technology/Nanoscale materials/Two-dimensional materials

Physical sciences/Nanoscience and technology/Nanoscale materials/Electronic properties and materials

2D semiconductors have attracted extensive research interest in recent years because of their excellent electrical and optical properties with atomically thin thickness, which has laid the foundation for continuing transistor scaling and exploring the next generation of electronic devices^1-5. Over the past decade, the 2D materials community has achieved pioneering advances in proof-of-concept demonstrations and synthesizing wafer-scale crystalline film^6-12. Currently, a principal challenge in transitioning 2D electronics from lab to industrial scale integrated circuits (ICs) is achieving high uniformity and yield in high-throughput electronic manufacture. This difficulty primarily stems from the introduction of chemicals and polymer residues on atomically thin 2D semiconductors surface during device manufacturing, which act as source of scattering or doping effects that disrupt the electrical properties of 2D channels, ultimately reducing the uniformity and yield of large-area electronic devices.

Patterning technique, which involves dividing large-area thin film into independent functional units, is a critical prerequisite for achieving complex logic functions and advancing ICs. Currently, the mainstream patterning processes for 2D material community follow traditional fabrication techniques such as photolithography for masks and reactive ion etching (RIE) for patterns. However, although these techniques are robust for traditional bulk materials, they are the dominant source of contaminating 2D surface and reducing uniformity in device manufacturing¹³. Specifically, the residues of polymer or chemicals on the delicate surfaces of 2D materials will reduce their electrical and optical performance^14-16. Furthermore, the cross-linking effect caused by plasma on the polymers mask could exacerbate this issue^17,18, posing significant challenges to the uniformity, repeatability and yield of large-scale 2D electronics and ICs.

To minimize the damages introduced by the patterning process to 2D materials, considerable efforts have been invested in optimizing masks or upgrading patterning tools to reduce the residues of chemicals and polymers. Early attempt introduced a buffer layer between the photoresist mask and 2D channel, which improved the removal efficiency of the photoresist mask¹⁹. However, this wet process could not completely eliminate chemical reagents and polymer residues to achieve an intrinsically clean 2D surface. Alternatively, direct laser patterning²⁰ and scanning probe patterning^21-23 techniques have been developed to directly etch 2D materials by avoiding the introduction of photoresist masks. Nevertheless, issues such as thermal accumulation in 2D materials caused by high-energy laser focusing and the excessive time-consumption of wafer-scale patterning have hindered their application in large-scale ICs. These non-optimized patterning results present critical challenges in the fabrication of high-quality, reliable electronic devices and advancing the industrialization of 2D semiconductors.

Inspired by ancient movable type printing²⁴ and modern nanoimprint technology^25,26, we develop a metal-stamp imprinting method for residue-free patterning of wafer-scale 2D materials. With predesigned 3D metal-stamp is physically pressed onto 2D film, the strong metal-2D interaction in the local contact region ensure 2D exfoliating from the substrate, while the 2D arrays in the non-contact region remains undamaged on the substrate. This physical patterning process avoids the use of any photoresists and chemical reagents, enabling wafer-scale, time-saving, and high-quality patterning of 2D materials. In addition to the direct verification of the atomic cleanliness and crystal of the obtained 2D arrays surface through photoluminescence (PL) spectroscopy, Raman spectroscopy, atomic force microscopy (AFM), and scanning transmission electron microscopy (STEM), we also fabricated 100 back-gated field-effect transistors (FETs) for transport measurement. These devices exhibited improved electrical performance and uniformity compared to those samples using traditional patterning method. Furthermore, we prepared wafer-scale logic circuits with a top-gated structure compatible with industrial fabrication process, demonstrating a high yield of 97.6% across 500 functional units. Our research overcomes the contamination issues associated with large-scale patterning of 2D materials, facilitating the production of uniform, high-yield electronic devices. Additionally, the intrinsic-clean 2D surface and edges provide a foundation for other research, such as large-scale heterogeneous integration^27,28, confined secondary growth^29,30 and monolithic 3D integration^31,32.

Figure 1 shows the fabrication process of our residue-free direct imprinting method. First, a thick SiO₂ array (1 μm) is prefabricated on a polished silicon substrate as 3D mold (Fig. 1a, i and Fig. 1b,h), using the standard photolithography and electron beam deposition process (Methods and Supplementary Fig. 1). Subsequently, the metal-stamp can be fabricated by depositing functional Au layer (50 nm) and spin-coating a supporting PC polymer layer on the 3D SiO₂ mold surface layer-by-layer (Fig. 1a, ii). The metal-stamp can then be directly mechanically peeled off from sacrificial Si substrate to inherit the inverted 3D morphology of prefabricated mold (Fig. 1c,i), which is also verified by AFM measurements (Fig. 1f,g). Next, the metal stamp is directly pressed on top of a CVD synthetic MoS₂ film (Fig. 1j), where the 3D stamp forms a local contact model with the bottom 2D film. The contact regions form a strong interface binding (between Au and MoS₂) due to the high adhesion energy at Au/S interface (highlighted by the blue box in the inset of Fig. 1d)^33-37, which provide enough strength to physically exfoliated local MoS₂ from grown substrate. In contrast, the dented region of 3D stamp cannot contact the bottom 2D film (highlighted by the red box in the inset of Fig. 1d), ensuring that the non-contacted 2D material retains its intrinsic state (Fig. 1a, iii and Fig. 1d). After separating the metal stamp from 2D film, the monolayer MoS₂ in contact region would be peeled away by metal stamp, while monolayer MoS₂ in the non-contact region remains on substrate with original quality, together to obtain a scalable monolayer MoS₂ arrays (Fig. 1a, iv and Fig. 1e,k). Compared to traditional methods, our metal-stamp imprinting method does not involve any photoresist or solution process to 2D film, therefore it could maintain the intrinsic properties of the delicate 2D lattice. Our method avoids the issue of quality or uniformity reduction in 2D materials patterning process, which is suitable for the preparation of large-scale and high-yield electronics.

By predesigning different 3D metal-stamps, we could pattern various 2D arrays with different shapes or periods, including rectangle, square, circle, ribbon, Hall bars, alphabet characters (Fig. 2a,b and Supplementary Fig. 2). The monolayer nature of stamp patterned MoS₂arrays is confirm by its Raman frequency difference of 19.0 cm^-1 between the E′ peak (in-plane vibration) and A′ peak (out-of-plane vibration) and AFM measurement (Supplementary Fig. 3). Furthermore, PL mappings are conducted from stamp patterned MoS₂arrays, demonstrating uniform intensity and suggesting the patterned MoS₂ are uniform not only within each unit but also across arrays (Fig. 2c,d).

The quality of the stamp patterned monolayer arrays is comparable to as-grown monolayer film and much better than traditional RIE method, as evidenced in the surface characterization of AFM and the crystal quality characterized by STEM and PL spectrum. As shown in Fig. 2e,f, the stamp patterned MoS₂flake demonstrates a pristine clean surface consistent with as-grown MoS₂film with a root-mean square (RMS) roughness of 0.4 nm, indicating the residue-free surface using our patterning method. Furthermore, we performed atomic-resolution high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) characterization for our stamp patterned MoS₂, demonstrating delicate lattice without damage or contaminations (Fig. 2g and Supplementary Fig. 4). In contrast, the traditional RIE patterned MoS₂ shows random impurities on 2D surface and substrate with the RMS of 3.8 nm (Fig. 2h,i), suggesting the photoresist and solution process of traditional RIE patterning method would leave unavoidable residues.

Next, we perform PL spectrum measurements to further quantify the optical quality and uniformity of patterned samples from different methods. As shown in Fig. 2j, our stamp patterned MoS₂shows similar PL curve with the as-grown film (6000 intensity and 670 nm peak), verifying that this dry patterning process is non-damaging to the 2D materials. In great contrast, the traditional RIE patterned samples show much decreased PL intensity (3500 intensity) and shifted PL peak (682 nm peak) by residues or strain generation, indicating its optical properties is decreased by this wet patterning process. Subsequently, we randomly test PL spectrum from 200 independent samples and statistically analysis the peak and intensity respectively (Fig. 2k,l). The stamp patterned samples demonstrate better optical quality and higher uniformity than traditional RIE method. We note that the original CVD MoS₂films for above two patterning methods are derived from one chip, and the measurement parameters are kept constant for a fair comparison (see Methods for more details).

With large-scale MoS₂on SiO₂/Si substrate synthesized by CVD, we could directly pattern film into individual monolayers and fabricate back-gated transistor arrays (see Methods for details). Figure 3a shows the optical image of large-scaletransistor arrays, and a semimetal bismuth (Bi) is used as source and drain contact electrodes³⁸, highly doped silicon and 280 nm SiO₂ is used as the back gate. As shown in Fig. 3b,c, the I_ds−V_gs transfer curves (where I_ds is the drain-source current and V_gs is the gate-to-source voltage) show n-type behavior and on/off ratio of 10⁸. The I_ds−V_dsoutput characteristics (V_ds is the drain-source bias) show linear behavior, indicating near ohmic contact between source/drain metal and monolayer MoS₂channel. To systematically explore the uniformity of scalable electronics, we characterize the electronic properties of 100 randomly selected MoS₂ transistors by our stamp patterning and 100 devices by traditional RIE method (as control samples) on one chip, and all be fabricated with same channel length/width of 5/10 μm (Fig. 3d and Supplementary Fig. 5). Although all transistors exhibit n-type conductive behavior, the samples prepared by our stamp patterning (red lines) show significant advantages in terms of electronic performance and uniformity over traditional RIE method (blue lines). Specifically, a statics histogram analysis of the threshold voltage (V_th, defined as I_ds of 0.1 nA/μm) demonstrates that the V_th in traditional method device (peak of V_th= -46 V) is more negative and its variation spread (Standard Error, σ = 2.125) is about 20 times higher than that in our stamp patterned MoS₂devices (V_th= -28 V, σ = 0.108), which largely attributed to the doping effect and uncontrollable quality degradation by polymer residues during traditional RIE process (Fig. 3e). Subsequently, the on/off ratio and carrier mobility are further extracted and analyzed respectively (Fig. 3f). Our stamp patterned devices exhibit high performance and narrow distribution of on/off ratio (I_on/I_off) of ~10⁸ (σ = 0.023) and mobility of 18.8 cm² V^-1 s^-1 (σ = 0.542) (highlighted by the green area), while the control devices show lower quality and larger variation of I_on/I_off~10⁶ (σ = 0.158) and mobility of 7.5 cm² V^-1 s^-1 (σ = 1.937) (highlighted by the orange area). Above comparison verified that our stamp patterning method can retain a residue-free and high-quality 2D crystal than traditional RIE method, ensuring that the fabricated large-scale transistors with higher electrical performance and uniformity.

To demonstrate the potential of metal-stamp patterning method in industrial high-volume production, we fabricated a variety of basic logic circuit arrays on a 2-inch wafer with stamp patterned MoS₂ (Fig. 4a). The wafer is divided into four functional areas, including FET (region #1), NMOS NOT (region #2), NAND (region #3) and NOR (region #4) logic gates (Fig. 4b,c). For the top-gated MoS₂ FET, the source /drain electrode (Bi/Au), top dielectric (Al₂O₃) and gate electrode (Cr/Au) is fabricated after MoS₂ channel patterning (see Methods for more details), and the I_ds−V_gs transfer characteristic shows n-type behavior; We fabricate the logic NOT gate by integrate two adjacent FETs, and the device generates a low voltage (off-state) when a positive voltage is loaded in V_in, while the device turns to high voltage (on-state) when a negative voltage is loaded, together leading to the NOT logic; We fabricate the NAND and NOR logic gates by integrating more top-gated FETs, also achieved correct logic functions and rail-to-rail conversion (Fig. 4d). Furthermore, we individually tested 200 top-gated FET (region #1) and 300 logic gates (region #2 to #4) on this wafer, and then obtained the device yield mapping. As shown in Fig. 4e, the green and red squares represent the functional and failed units respectively, demonstrate reliable device function and achieve a high yield of 97.6%. The above successful construction of basic logic gates shows that stamp patterned 2D materials are suitable for various electronics, and the high yield demonstrates the exciting potential of our patterning method for future ICs development.

In summary, we report a residue-free imprinting method for the facile patterning of wafer-scale 2D materials by using a 3D metal-stamp. The surface cleanness and optical quality of our stamp patterned MoS₂ arrays are consistent with that of as-grown intrinsic crystal film, as confirmed by the AFM, PL and STEM characterization. Furthermore, we have shown that this stamp patterning method can be used to fabricate large-scale transistors and logic circuits, with higher performance, superior uniformity (20 times lower standard error in V_th) and high yield of 97.6% compared to that of traditional RIE method. Our simple method provides a high-throughput patterning technology that overcomes the challenge of 2D lattices being contaminated or damaged by traditional methods, and provides a practical patterning idea for ultra-thin materials (2D or 3D) with delicate lattices. We anticipate that the intrinsically high-quality 2D arrays obtained by this method will also be conducive in both academic and industrial field, including novel twisted moiré superlattice^27,28, monolithic 3D integration^31,32,39 and 2D materials towards industrialization^40,41.

Metal stamp fabrication and patterning process

First, photolithography is conducted on a polished Si wafer to pattern the mold structure, followed by the electron beam deposition (or sputtering) of a 1 μm thick SiO₂ film (deposition rate ∼1 Å s⁻¹) and lift-off in hot acetone (Supplementary Fig. 1a and Fig. 1h). Next, 50 nm thick Au film (thermal evaporation rate ∼0.5 Å s⁻¹) is deposited (Supplementary Fig. 1b), followed by spin-coating a 10 wt % PC (Aldrich, molecular weight ∼45 000 g/mol) layer on the surface of 3D SiO₂ mold with a speed of 3000 rpm for 60 s and baked at 100 °C (3 min). With the PI tape+PDMS supporting layer, Au and PC films can be peeled-off from the Si substrate and flipped onto the surface of glass+metal frame to prepare the Au-stamp (Supplementary Fig. 1c), which inherit the inverted 3D morphology of prefabricated mold. Immediately, the 3D Au stamp is then pressed onto the surface of the as-grown 2D film and is heated at 120 °C for 5 min. After separating the stamp, large-area MoS₂ arrays can be observed on substrate.

For control samples with traditional RIE method, photoresist (micro resist technology, S1850) is spin-coated onto as-grown 2D film with a speed of 6000 rpm for 60 s and baked at 110 °C (3 min), followed by the photolithography is conducted to fabricated mask patterns. Next, RIE (O₂) is conducted to etching the samples (power of 50W, 10s), followed by soak in hot acetone (60 °C, 1h) to remove the photoresist mask and then MoS₂ arrays is obtained.

PL and Raman characterizations

The prepared samples are placed on a confocal microscope (WITEC alpha 200R) to measure Raman and PL spectra. For PL spectrum measurement, a 532 nm laser with 1800 lines mm⁻¹ grating is used, and laser power is 0.6 mW. For Raman spectrum measurement, a 532 nm laser is used with 1 mW power and a grating level of 2400 lines mm⁻¹.

Monolayer MoS₂ FET arrays fabrication

After patterning MoS₂ arrays on grown SiO₂/Si substrate (dielectric/back gate), photolithography is conducted to pattern the source/drain electrodes (TuoTuo Technology (Suzhou) Co., Ltd.), followed by deposition of Bi/Au (20 nm of Bi, 50 nm of Au) using a thermal evaporation system under vacuum (pressure ∼10⁻⁷ Torr) and lift-oﬀ. For fair comparison, the original CVD MoS₂ films for two patterning methods are derived from one chip, and the device fabrication and measurement parameters are kept constant.

Wafer-scale logic circuits fabrication

After patterning MoS₂ arrays on grown 2-inch sapphire substrate, first photolithography is conducted to pattern the source/drain electrodes, followed by deposition of Bi/Au (20 nm of Bi, 30 nm of Au) and lift-off. Next, Atomic layer deposition (ALD) is conducted to deposit high-κ gate dielectric (20 nm Al₂O₃) at 150 °C using trimethyl aluminium and water as precursors. The via of the gate dielectric layer is realized by second photolithography and solution-etching of Al₂O₃ by NaOH. Last, third photolithography is conducted to pattern the top gate electrodes, followed by deposition of Cr/Au (2 nm of Cr, 50 nm of Au) and lift-off. The electronic measurement of wafer-scale logic gates is conducted in air using Keithley 4200A semiconductor analyzer.

Data availability

All data are available in the main text or the supplementary materials.

Acknowledgments:

This work is supported by ASTAR (M21K2c0116, M24M8b0004), Singapore National Research foundation (NRF-CRP22-2019-0004, NRF-CRP30-2023-0003, NRF2023-ITC004-001 and NRF-MSG-2023-0002) and Singapore Ministry of Education Tier 2 Grant (MOE-T2EP50222-0018).

Author contributions:

W.G. and Zhiwei L. conceived the project. Zhiwei L. performed the experiments and data analysis. Xiao L. contributed to PL and transistor measurements. J.S. contributed to photolithography and logic gates fabrication. X.C. contributed to STEM characterization. Y.Z. contributed to schematics drawing. W.C., Y.J., C.Z., Y.D., Y.L., X.W., H.C., and Zheng L. contributed to devices fabrication. T.L. provide the wafer monolayer MoS₂ film. W.G. and Zhiwei L. co-wrote the manuscript. All authors discussed the results and commented on the manuscript. Zhiwei Li and Xiao Liu contributed equally to this work.

Competing interests:

The authors declare no competing financial interests.

Chhowalla, M., Jena, D. & Zhang, H. Two-dimensional semiconductors for transistors. Nat. Rev. Mater. 1, 16052 (2016).
Qiu, H. et al. Two-dimensional materials for future information technology: status and prospects. Sci. China Inf. Sci. 67, 160400 (2024).
International Roadmap for Devices and Systems 2023 Edition (IEEE, 2023).
Liu, Y. et al. Promises and prospects of two-dimensional transistors. Nature 591, 43-53 (2021).
Liu, Y., Huang, Y. & Duan, X. Van der Waals integration before and beyond two-dimensional materials. Nature 567, 323-333 (2019).
Li, W. et al. Approaching the quantum limit in two-dimensional semiconductor contacts. Nature 613, 274-279 (2023).
Tan, C. et al. 2D fin field-effect transistors integrated with epitaxial high-k gate oxide. Nature 616, 66-72 (2023).
Xia, Y. et al. 12-inch growth of uniform MoS₂ monolayer for integrated circuit manufacture. Nat. Mater. 22, 1324-1331 (2023).
Li, T. et al. Epitaxial growth of wafer-scale molybdenum disulfide semiconductor single crystals on sapphire. Nat. Nanotechnol. 16, 1201-1207 (2021).
Qin, B. et al. Interfacial epitaxy of multilayer rhombohedral transition-metal dichalcogenide single crystals. Science 385, 99-104 (2024).
Liu, L. et al. Transferred van der Waals metal electrodes for sub-1-nm MoS₂ vertical transistors. Nat. Electron. 4, 342-347 (2021).
Li, W. et al. Monolayer black phosphorus and germanium arsenide transistors via van der Waals channel thinning. Nat. Electron. 7, 131-137 (2023).
Liu, S. et al. Nanopatterning technologies of 2D materials for integrated electronic and optoelectronic devices. Adv. Mater. 34, e2200734 (2022).
Mondal, A. et al. Low Ohmic contact resistance and high on/off ratio in transition metal dichalcogenides field-effect transistors via residue-free transfer. Nat. Nanotechnol. 19, 34-43 (2024).
Zhao, Y. et al. A clean transfer approach to prepare centimetre-scale black phosphorus crystalline multilayers on silicon substrates for field-effect transistors. Nat. Commun. 15, 6795 (2024).
Nakatani, M. et al. Ready-to-transfer two-dimensional materials using tunable adhesive force tapes. Nat. Electron. 7, 119-130 (2024).
Mao, H., Wu, D., Wu, W., Xu, J. & Hao, Y. The fabrication of diversiform nanostructure forests based on residue nanomasks synthesized by oxygen plasma removal of photoresist. Nanotechnology 20, 445304 (2009).
Franquet, A. et al. Characterization of post-etched photoresist and residues by various analytical techniques. Appl. Surf. Sci. 255, 1408-1411 (2008).
Choi, A. et al. Residue-free photolithographic patterning of graphene. Chem. Eng. J. 429, 132504 (2022).
Poddar, P. K. et al. Resist-free lithography for monolayer transition metal dichalcogenides. Nano Lett. 22, 726-732 (2022).
Garcia, R., Knoll, A. W. & Riedo, E. Advanced scanning probe lithography. Nat. Nanotechnol. 9, 577-587 (2014).
Albisetti, E. et al. Thermal scanning probe lithography. Nat. Rev. Methods Primers 2, 32 (2022).
Wei, Z. et al. Scratching lithography for wafer-scale MoS₂ monolayers. 2D Mater. 7, 045028 (2020).
Hummel, A. W. Movable type printing in China: a brief survey. Quarterly Journal of Current Acquisitions 1, 18–24 (1944).
Maruyama, N. et al. Advances and applications in nanoimprint lithography. Novel Patterning Technologies 12497, 124970D (2023).
Asano, T. et al. The advantages of nanoimprint lithography for semiconductor device manufacturing. Proc. of SPIE 11178, 111780I (2019).
Lian, Z. et al. Valley-polarized excitonic Mott insulator in WS₂/WSe₂ moiré superlattice. Nat. Phys. 20, 34–39 (2024).
Tan, Q. et al. Layer-dependent correlated phases in WSe₂/MoS₂ moiré superlattice. Nat. Mater. 22, 605–611 (2023).
Kim, K. S. et al. Non-epitaxial single-crystal 2D material growth by geometric confinement. Nature 614, 88-94 (2023).
Li, J. et al. General synthesis of two-dimensional van der Waals heterostructure arrays. Nature 579, 368-374 (2020).
Lu, D. et al. Monolithic three-dimensional tier-by-tier integration via van der Waals lamination. Nature 630, 340-345 (2024).
Guo, Y. F. et al. Van der Waals polarity-engineered 3D integration of 2D complementary logic. Nature 630, 346–352 (2024).
Huang, Y. et al. Universal mechanical exfoliation of large-area 2D crystals. Nat. Commun. 11, 2453 (2020).
Liu, F. et al. Disassembling 2D van der Waals crystals into macroscopic monolayers and reassembling into artificial lattices. Science 367, 903–906 (2020).
Ding, S. et al. Ag-assisted dry exfoliation of large-scale and continuous 2D monolayers. ACS Nano 18, 1195-1203 (2024).
Fu, Q. et al. One-step exfoliation method for plasmonic activation of large-area 2D crystals. Adv. Sci. 9, e2204247 (2022).
Li, Z. et al. Dry exfoliation of large-area 2D monolayer and heterostructure arrays. ACS Nano 15, 13839-13846 (2021).
Shen, P. C. et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature 593, 211-217 (2021).
Jayachandran, D. et al. Three-dimensional integration of two-dimensional field-effect transistors. Nature 625, 276–281 (2024).
Kim, K. S. et al. The future of two-dimensional semiconductors beyond Moore’s law. Nat. Nanotechnol. 19, 895–906 (2024).
Milana, S. The lab-to-fab journey of 2D materials. Nat. Nanotechnol. 14, 919–921 (2019).

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Residue-free wafer-scale direct imprinting of two-dimensional materials

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Abstract

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Introduction

Residue-free direct imprinting of 2D film

Characterization of MoS2 array

High-uniformity of MoS2 transistor arrays

High-yield of wafer-scale logic circuits

Discussion and outlook

Methods

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References

Additional Declarations

Supplementary Files

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