The comparison between the drain current characteristics of conventional DL and JL and high-k/vacuum dielectric based DL and JLFETs is shown in Fig. 2 (a-b-c). It is observed, the drain current (Ion) of vacuum DL and JLFETs are degraded by 25 % and 30% in comparison with conventional DL and JLFET. Whereas the drain current of vacuum HDL-JLFET and HJLFET is degraded by 20.05% and 2%, respectively. Hence, the improvement in drain current of vacuum HDL-JLFET is higher than vacuum based HJLFET, DL-JLFET and JLFET. This improvementin drain current of vacuum HDL-HLFET is obtained due to combination of high-k dielectric near the source side Fig. 2 - Drain current characteristics of (a) conventional DL and JL, (b) VacuDL and VacuJL, and (c) VacuHDL and VacuHJL at VDS = 1 V and VGS = 1 V.
and hafnium metal electrodes at S/D contact which enhances the transport efficiency and electron plasma. In addition, the lightly doped channel in HDL-JLFET reduces leakage current (Ioff). Hence, the overall performance of HDL-JLFET in terms of I on/Ioff is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL-JLFET, HJLFET and JLFET, as summarized in Table-I and table-II.
Parameters | JL | VacuJL | VacuHJL |
Ion/Ioff | 7.6× 106 | 2.4× 106 | 4.9× 106 |
Cgg(fF) | 0.79 | 0.53 | 0.55 |
τ(pS) | 0.96 | 0.92 | 0.88 |
CHC Degradation | 20.05 % | 14 % | 17.5 % |
TABLE I. COMPARISON OF PURSURANCE METRICS AND CHC DEGRADATION OF CONVENTIONAL JLFET, VACUUM JLFET, AND VACUUM HJLFET. |
Parameters | DL | VacuDL | VacuHDL |
Ion/Ioff | 1.82× 108 | 0.21× 108 | 0.95× 108 |
Cgg(fF) | 0.51 | 0.31 | 0.39 |
τ(pS) | 0.49 | 0.42 | 0.38 |
CHC Degradation | 10.4 % | 6.0 % | 6.9 % |
TABLE II. COMPARISON OF PURSURANCE METRICS AND CHC DEGRADATION OF CONVENTIONAL DL-JLFET, VACUUM DL-JLFET, AND |
VACUUM HDL-JLFET.
From Table I and II, it is summarized that the total gate capacitance (Cgg) decreases with the incorporation of vacuum dielectric in DL and JLFETs as compared to conventional dielectric DL and JLFETs. However, the Cgg of vacuum DLJLFET is lower than the vacuum HDL-JLFET, in spite of that the intrinsic delay of HDL-JLFET is improved by 9.5% in comparison with vacuum DL-JLFET. Because, the intrinsic delay of FET is approximated as CggVds/Id and here, in case of vacuum HDL-JLFET, the rate of increase in capacitance is compensated by amount of increase in drain current, hence, the intrinsic delay of vacuum HDL-JLFET is lower than vacuum DL-JLFET. On the other hand, the gate capacitance of other vacuum dielectric based JLFETs is higher than HDL-JLFET. Hence, the intrinsic delay of HDL-JLFET is improved by 56.8 % and 58.7 %, respectively, in comparison with vacuum based HJLFET and JLFET, as summarized in Table I and II. Thus, the lower intrinsic delay and higher Ion/Ioff ratio of vacuum HDL-JLFET will show better switching performance and make it the most suitable candidate for high speed digital circuit applications.
The degradation in drain current of conventional and vacuum/ high-κ dielectric DL and JLFETs under CHC stress of 2000s. It can be observed from Table I that the conventional dielectric DL and JLFETs experience higher drain current degradation (10.4 % and 20.5 %) as compared to vacuum HDL-JLFET and HJLFET (6.9 % and 17.5 %). Whereas, the drain current of only vacuum dielectric DL and JLFETs are degraded by 6 % and 14 %. The lower drain current degradation is observed with vacuum DL and JLFETs due to lower electric field at the drain side Fig. 3 - Electric field profile of (a) conventional DL-JLFET, vacuum DLJLFET, and vacuum HDL-JLFET, (b) conventional JLFET, vacuum JLFET, and vacuum HJLFET under CHC stress for 2000 seconds at VD = VG = 1.9 V.
Figure 4 - Threshold voltage variation of (a) conventional DL-JLFET, vacuum DL-JLFET, and vacuum HDL-JLFET, (b) conventional JLFET, vacuum JLFET, and vacuum HJLFET under CHC stress for different time spans at V D = VG = 1.9 V.
and hence the fewer probability to occur the impact ionization process driven by electrical bias, as shown in Fig. 3 (a) and (b). Thus, the vacuum DL and JLFETs are more immune from short channel effects (SCEs) in contrast with conventional DL and JLFETs. Moreover, fabrication of high-k dielectric on top of silicon directly may cause defects in the interface of these two layers and adversely can affect the channel formation inside the silicon [18]. Due to this defect, influence occurs in drain current of both the device (vacuum DL and JLFETs). But, here, we have considered the most damaging CHC stress condition near the drain side in both devices and this effect in short channel devices is mainly caused by the SCE not by the presence of high-k layer [11]. Hence, the CHC induced degradation is less pronounced in vacuum HDL-JLFET and HJLFET as compared to conventional DL and JLFETs. Similarly, the lower degradation was obtained with vacuum DL and JLFETs due to much lower electric field near drain side. It can be seen from Fig. 3 (a) and (b), the lower electric fields are observed near the drain side in the channel in high-k/vacuum dielectric based DL and JLFETs as compared to conventional DL and JLFETs. Hence, the short channel effect (SCE) is insignificant with vacuum dielectric based DL and JLFET and it is more immune from CHC stress. It is also summarized in Table I and II.
From the Fig. 4 (a-b), variation in threshold voltage is observed and lead to enhancement in it under CHC stress at VD = VG = 1.9 V and it is less pronounced in high-κ/vacuum dielectric DL and JLFETs in comparison with conventional dielectric DL and JLFETs. Hence introduced vacuum dielectric near the drain side reducing electric field as a reuslt minimizing the effect of impact ionization. Moreover, the possibilities of damaging the dielectric are now reduced since hot carriers are now dealing directly with gate electrode. It is just due to decrement in traping inside the dielectric. One can also observe from Fig. 4 (a) that the DL structures show less Vth variability due to CHC stress in comparison to JLFET based structures. In addition, drain current degradation results in an increment in density of states and hence the threshold volage. Drain current of DL-JLFET is comparatively very low than the drain current of JLFET, it may be as a result of the reduction in doping concentration, electric field and density of interface states. Hence, the combination of CP with vacuum dielectric based HDL-JLFET and DL-JLFET show more immunity against CHC induced stress.