Design and implementation of  CSVCO for PLL applications

doi:10.21203/rs.3.rs-5346700/v1

This paper depicts the design and performance analysis of Current Starved Voltage Controlled Oscillator (CSVCO), With different low leakage power techniques. This low power techniques of CSVCO is implemented in Phase Locked Loop by achiving the various field of applications, which are suitable to show efficient result of PLL for fast locking system, such as Frequency synthesizer, Multiplier and Frequency control, Tracking generators, Clock generation and recovery system etc. The proposed work sleep stack technique CSVCO which consumes low power, Less Area, Low Phase Noise, Less Delay, Also achieving higher frequency tuning range. Low power consumption gives significantly higher efficiency of PLL. This CSVCO simulation work is performed about the parameters of the phase noise is -63.8 dBc/Hz with supply voltage 0.45V and frequency of 2.759GHz. Power (mw) 0.002559, Delay(µs) 0.0006544. Complete work done by using cadence virtuoso 45NM CMOS technology.

Electronic Materials and Devices

Electrical Engineering

Optical Materials and Devices

Magnetics Materials and Devices

Systems Engineering

Control Voltage

Current Starved Voltage Controlled Oscillator

Gal-or

Lector

Phase noise

Phase Locked Loop

Oscillation-frequency

Sleep stack

Tuning Range

Nowadays, in advance PLL two different categories of VCO, CSVCO and SCVCO (Source Coupled Voltage Controlled Oscillator) are used. Recent studies show LC oscillators also have low power consumption as well as good phase noise performance. But they also have some drawbacks such as First, the tuning range of LC Oscillators are low as compared to ring oscillators and Second, the quality of on chip spiral inductors mainly decides the phase noise performance of Oscillators, which is not easy to be achieved. However, Ring oscillators have no such complication of spiral inductors like LC Oscillators. Thus they occupy less area. In this paper mainly focus on the design technique of a low power CSVCO with 1V of voltage supply which also has less area and low phase noise with high oscillation frequency.The development of fast and efficient technology relies heavily on high-speed devices. The design of analog circuits in mixed-signal systems is constrained by switching noise, which occurs when analog anddigital circuits are integrated onto the same chip. CMOS circuits have high levels of switching noise, making them less desirable for modern circuits. Hence Current Mode Logic (CML) circuits are generally preferred by Sivasakthi M (2023)[1]. Optimized the VCO to enhance the performance of PLL in various ways Jin J (2018)[2]. However, the tuning range of VCO is often limited. All of the techniques mentioned earlier share a common disadvantage. By utilizing positive feedback is an advantage because it aids in adjusting the frequency tuning range Various methods have been employed to achieve a broad tuning range by Rajalingam P (2020)[3].

In order to achieve minimum phase noise at all conditions of frequencies a process variation tolerant PLL is designed with adaptive duty cycle control strategy technique. It is used to attain lock condition quickly One of the techniques discussed a differential VCO that has a maximum consumption of power but with minimum phase noise Current starved VCO (CSVCO)with the Dynamic threshold voltage MOSFET (DTMOS) technique is used for efficient switching and high oscillation frequency. In this, gate and body terminals are connected which vary the body and gate voltage results in minimized sub threshold leakage current CS sleep VCO provides maximum tuning range with reduced area. It also concentrates on low power consumption Rajalingam P (2021)^[4] But current starved sleepy stack voltage controlled oscillator provides immense power reduction and maximum tuning range than others

Sushmita Verma (2016) ^[5] a design of low power, low phase noise CMOS three stage Current starved Voltage Controlled Oscillator (CSVCO) using 45nm CMOS technology.Finally, the comparison of the present work with the earlier published work has been done and the improvements are observed. Suraj Kumar Saw (2015)^[6], Current starved CMOS VCO with an ultra low power and low phase noise have been proposed. Power dissipation and circuit area are very less making it useful for wireless devices. Phase noise and transient response have been performed at 1MHz and phase noise comes out to be -104.0dBc/Hz with supply voltage of 1V. Deepak Balodi (2017)^[7], in this paper, frequency analysis of CSVCO and DAVCO has been done with 350 nm CMOS technology. Various parameters like tuning range, frequency response, and power dissipation of CSVCO and DAVCO has been compared under same environment. Shruti Suman (2016)^[8], PLL has been designed using ring VCO at supply voltage 3V with 180 nm CMOS technology. Proposed ring VCO has been used for implementation of PLL in GHz frequency range. Power dissipation of PLL is 28 MW with frequency of 2.5 GHz. Pothina, C.K(2023)^[9] In their study to reduced number of transistors with a reduced area in proposed design with very low power consumed at DC voltage of 1.8 V. The Total Power Consumed by the proposed PLL design is 194.24 micro-Watts. We know that the power consumed, the sizing of the transistors, and the selection of the power supply voltage at different levels may vary with the total power consumed, respectively.Ghasemian, M.S.P.H (2021)^[10] in this work, a modified integrator is introduced into the path of the in-quadrature signal to generate another in-phase component with much lower harmonic content. The proposed method imposes only a small computational burden on the existing SOGI-PLL compared to the previously presented methods that address the input voltage harmonic problem. Moreover, this method can work properly within the allowable range of grid voltage frequency deviations.Gong, H.; Wang, (2021)^[11] In their study to the current controller for grid-connected voltage-source converters (VSCs), considering the dynamic impacts of the phase-locked loop (PLL), weak grids, and of voltage feed forward (VFF) control. First, a single-input single-output transfer-function-based model is proposed to characterize the interactions of control loops.Sánchez-Herrera (2022) ^[12] To introduces a new, easy, fast and highly efficient PLL algorithm, that it does not need to adjust every time the input signal changes. This makes it independent of the input signal it receives and, therefore, and in a certain way, universally applicable. In addition, the proposal is implemented exclusively by software, housed in a micro controller, which also represents another novelty.

The proposed current starved ring based VCO with sleep stack technique mitigates phase noise, area,power and delay.To minimize sub threshold leakage power in the proposed circuit, The CSVCO circuit is implemented with sleep Stack technique in which both the stack and sleep techniques are implemented above and below the pull up and pull down network respectively. In normal mode, the sleep transistor would go to sleep mode, then the stack transistors reduce the leakages [13–15]. In case of the active mode the sleep transistor becomes ON and stack transistors are OFF, reducing the leakages in CSVCO circuit.

3.1 Sleep stack technique implemented in CSVCO

The basic CSVCO is operated with the input voltage namely control voltage (Vctrl). As the Vctrl decreases, the current that is to be mirrored from the transistor M1 reduces when it is passed through the different PMOS in the delay stages. Because of the active mode of transistors in the CSVCO the leakage power has been increased [1].

In this paper, the current starved VCO has been implemented with different low power leakage techniques like Gale-or, Lector, Sleepy Keeper, Sleep, Stack and Sleepy Stack to observe the better performance of the circuit [12] Performance analysis can be observed in terms of different parameters like frequency,delay and average power are calculated in different process corners showing the improved performance Phase Locked Loop, For different applications. The CSVCO circuit is implemented with Stack technique as shown in Fig. 6, in which both the stack and sleep techniques are implemented above and below the pull up and pull down network respectively. In normal mode, the sleep transistor would go to sleep mode,then the stack transistors reduce the leakages[24–26]. In case of the active mode the sleep transistor becomes ON and stack transistors are OFF, reducing the leakages in CSVCO circuit.

In sleep stack technique, both the transistors PMOS & NMOS are implemented in two modes of operation.During the normal mode the sleep transistor is goes to sleep mode, in this case the stack transistor reduce the leakage power. Active mode of operating the sleep transistor gets ON and stack transistor goes to OFF condition, which reducing the leakage power in CSVCO circuit [23]. CSVCO with sleep Stack technique implemented in different stages of csvco like 5,7 and 9- stages and calcutaed the different parameters, among all the techniques of low power the simulation work shows the efficient result that was applied in phase locked loop architecture with VCO block.

3.2 Current starved VCO PLL architecture with sleep stack technique

Analysis of cause within wireless network technology involves investigating the underlying reasons for performance issues or failures. It examines factors like signal interference, hardware malfunctions, and network congestion that can impact connectivity and efficiency. By delving into these causes, solutions can be developed to enhance reliability and optimize network performance.

Among the different types of V CO's, ring oscillator is the efficient in terms of frequency and driving capabilities. The ring VCO has been designed with delay stage. These delay stages further when increased lead to the non linearity of the circuit. This non linearity can be overcome by increasing the number of delay cells which has increased the complexity of the circuit and also increasing the power consumption [8]. The output frequencies of an basic VCO are controlled by the control voltage where as the current is controlled by the current starved VCO [9–10]. The circuit consists of delay cells along with the current mirror which is used to limit the current to all the delay cells. The current starved VCO alone together has also increased the leakages and power consumption [1]. These leakages can be further reduced by applying the low leakage techniques to the delay cells and by varying the aspect ratio of transistors which reduces the threshold voltage [11]. Basic current starved VCO, In order to avoid this power consumption an VCO named current starved was designed.

The simulation done by the Cadence Software in virtuoso tool with 45 NM Technology,The supply voltage is 0.45V. The performance of CSVCO with 5,7&9 stages applying with low leakage reduction techniques The output of oscillator is obtained by initializing the node either 1 or 0 to get proper oscillations. The parameter like average power(Pavg) is calculated at a room temperature of 27°C and with a control voltage of 0.45v.To analyze the simulation results and calculate the parameters like noise, frequency, delay using spectre simulator.

The provided graph illustrates the output noise power spectral density (PSD) of two CSVCO configurations: a conventional CSVCO and a Sleep Stack CSVCO. The x-axis represents the offset frequency from the carrier frequency, while the y-axis indicates the output noise power density in decibels relative to 1 Hz bandwidth (dBc/Hz).

Table 1

Comparison analysis of PLL CSVCO VS PLL CSVCO with Sleep Stack Technique
References	[21]	[22]	[23]	[24]	[25]	[26]	[19]	Ref	PLL with basic CSVCO	Proposed work-PLL with SLEEP STACK CSVCO
Tech(nm)	90	180	65	180	180	180	90	45	45	45
VCO type	VCDL	-	Ring	Ring	Ring	Ring	Ring	Ring	Ring	Ring
Freq(GHz)	2.55	5	0.35	5.6	5.32	1.37	3.63	0.0075	2.492	2.759
Supply volt(v)	1.2	1.2	0.4	1.8	1.8	1.8	1	1.8	1	1
Power(mw)	20	18.3	0.109	19.8	19.8	35	0.05	0.08163	0.002786	0.002559
P-Noise(dBc/Hz)	-127.4	-123.7	-90	-114.3	-110	-108	-80.75	-73.8	-72.2	-63.8
Delay(µs)	23.4	22	-	20	80	2.92	0.866	0.04147	0.866	0.0006544

Table 2

Simulation results for Parameters with different low leakage power techniques in CSVCO
S.No	Low Leakage Power Techniques	Average Power (W)	Area (µm2)	Delay (µs)	Frequency (GHz)	Gain (Ghz/V)	Tuning Range (%)
1	Gale-or	48.20 e-9	37.5769	19.56	13.81	3.07	56.21
2	Lector	49.77 e-9	35.581225	32.25	14.34	3.19	6.07
3	Sleep	40.45 e-12	26.3169	327.8	72.11	16.02	98.76
4	Stack	49.56 e-9	56.4001	19.03	30.45	6.76	14.71
5	Sleep Stack	48.32 e-9	37.5769	0.4896	58.89	13.87	34.86

Table 3

Comparison analysis of PLL CSVCO VS sleep stack PLL CSVCO
Parameters	PLL with basic CSVCO	Proposed work- PLL with SLEEP STACK CSVCO
VCO type	Ring	Ring
Tech(NM)	45	45
Freq(GHz)	2.492	2.759
Supply volt(v)	1	1
Power(MW)	0.002786	0.002559
P-Noise(dBc/Hz)	-72.2	-63.8
Delay(µs)	0.866	0.0006544

A bove figure compares the performance of two Phase-Locked Loop (PLL) configurations: one with a basic Current-Starved Voltage-Controlled Oscillator (CSVCO) and the other with a proposed "Sleep Stack" CSVCO. The x-axis lists various parameters, while the y-axis represents the values associated with each parameter. The Sleep Stack CSVCO represents a promising design approach for PLLs that prioritize low power consumption and reduced supply voltage requirements. However, the choice between the basic CSVCO and the Sleep Stack CSVCO will depend on the specific requirements of the application.

The proposed Sleep Stack technique offers a promising approach to improve the efficiency of CSVCOs for PLL applications. By dynamically adjusting the oscillator's operating mode, significant power savings can be achieved without compromising performance. The optimization techniques outlined in this paper can further enhance the efficiency and effectiveness of the Sleep Stack CSVCO.

From the above tabular column and the graphs plotted it is observed that all the low leakage power techniques applied to the existing CSVCO are better in one or the other parameter like average power, oscillation frequency, delay and the gain. It is also observed that as the temperature is increased from corner analysis 27℃ to 80℃then the power and delay are increased and they are decreased when the temperature is decreasedto-40℃.

After comparison of the various parameters of PLL implemented with Sleep Stack CSVCO and Basic CSVCO it is observed that Sleep Stack has better performance. To achieve further higher frequencies vary the supply voltage and the number of stages in the CSVCO i,e from 5 stages to 7,9,11 and so on but with increase in other parameters like area and power.

CONFLICTS OF INTEREST

The authors declare that they have no conflict of interest.

ACKNOWLEDGMENT

The authors would like to thank the Department of Electronics and Communication Engineering, Central Institute of tool design, Hyderabad, for providing the resources (EDA Lab – Cadence Virtuoso tool) to this research.

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The authors declare no competing interests.

FIGURES.docx

Design and implementation of CSVCO for PLL applications

Status:

Version 1

Abstract

Figures

1. INTRODUCTION

2. LITERATURE REVIEW

3. METHODOLOGY

3.1 Sleep stack technique implemented in CSVCO

3.2 Current starved VCO PLL architecture with sleep stack technique

4. SIMULATION RESULT & ANALYSIS

5. CONCLUSIONS & FUTURE SCOPE

Declarations

CONFLICTS OF INTEREST

ACKNOWLEDGMENT

References

Additional Declarations

Supplementary Files

Status:

Version 1