Different SRAM cell topologies including the conventional 6T, conventional 8T
(L. Chang, 2005)
, Schmitt-Trigger-based 10T (ST2) (Kulkarni, 2011), P-P-N-based cell core 10T (PPN10T) (Sanvale, 2019), single-ended feedback-cutting 11T (FC11T) (Ensan, 2018), Schmitt-Trigger-based 11T (ST11T) (Ahmad, 2016), and Schmitt-Trigger-based 12T (ST12T) (Tomar, 2020), as shown in Fig. 1, are investigated in this section. Table 1 compares the cell features of the SRAM cells. These SRAM cells are redesigned using FinFET devices and comprehensively compared in terms of major design metrics like stability factors and delay during the working modes, dynamic power, leakage power, and quality metric. For this reason, various HSPICE simulations at 7-nm predictive technology model multi-gate (PTM–MG) technology (P. T. M. (PTM)) has been done at LEVEL = 72, 25 ˚C temperature, and a certain range of supply voltage of VDD from 0.2 V to 0.5 V by a linear variation of 0.1 V. The effective width (W) of a FinFET is given in Eq. (1) as follows (Mahmoodi, 2020):
![](https://myfiles.space/user_files/83400_b9e2661d18ef2d4b/83400_custom_files/img1629300003.png)
in which Hfin is the fin height and Tfin is the fin thickness.
Transistor sizing plays a vital role in an SRAM cell design, which highly affects the RSNM and WSNM of that cell. This issue becomes significant in the 6T SRAM cell because of conflicting read/write requirements (Golipour, 2021). Therefore, in all the considered SRAM cells, an N = 2 and an N = 1 have been chosen for pull-down transistors and other remaining transistors, respectively (Ansari, 2015). A comparative analysis of different performance metrics is discussed in the following subsections.
Table 1. Feature comparison of various studied SRAM cells.
Cell Feature
|
6T
|
8T
|
ST2
|
PPN10T
|
FC11T
|
ST11T
|
ST12T
|
Transistor Count
|
6
|
8
|
10
|
10
|
11
|
11
|
12
|
Read/Write
|
Diffa /Diff
|
SEb /Diff
|
Diff/Diff
|
Diff/Diff
|
SE/SE
|
SE/SE
|
SE/Diff
|
Bitlines
|
(2)
BL-BLB
|
(3)
BL-BLB-RBL
|
(2)
BL-BLB
|
(3)
WBL-WBLB-RBL
|
(1)
BL
|
(2)
BL-RBL
|
(2)
BL-BLB
|
Control signals
|
(1)
WL
|
(2)
WL-RWL
|
(2)
WL-WWL
|
(2)
WL-RWL
|
(3)
WL-WWLA-WWLB
|
(3)
WL-RWL-VGND
|
(3)
WL-WLB-RWL
|
Read-disturb-free
|
No
|
Yes
|
No
|
Yes
|
Yes
|
Yes
|
No
|
Half-select-free
|
No
|
No
|
No
|
No
|
No
|
Yes
|
Yes
|
3.1 Stability Analysis
The stability is normally estimated as the static noise margin (SNM). The noise margin is characterized by plotting the overlapped voltage transfer characteristics (VTCs) (known as butterfly curves) for the cross-coupled inverters that make the latch of memory cells (Sanvale, 2019). The length of the biggest square which can be inscribed inside the smaller eye of the butterfly curve provides the noise margin (Gholipour E. A., 2020). Table 2 gives the SNM of the various SRAM cells in the hold, read, and write modes at VDD = 0.2 V.
Table 2. A static noise margin of the various SRAM cells during the hold, read, and write operations at VDD= 0.2 V.
Static noise margin
|
6T
|
8T
|
ST2
|
PPN10T
|
FC11T
|
ST11T
|
ST12T
|
HSNM (mV)
|
67.1
|
67.1
|
73.5
|
62.4
|
67.1
|
79.2
|
79.2
|
RSNM (mV)
|
32.8
|
67.1
|
46.3
|
62.4
|
67.1
|
79.2
|
44.1
|
WSNM (mV)
|
73.4
|
46.9
|
89
|
67
|
84.5
|
74
|
112.3
|
3.1.1. Hold Stability
Hold stability of an SRAM cell is gauged by the hold static noise margin (HSNM) and defined as the maximum DC noise voltage that the SRAM cell can stand without altering the data in the hold mode (He, 2019). HSNM is the side length of the maximum square which can fit in the smaller wing of the butterfly curve during the hold mode (Gholipour A. a., 2020). Fig. 2 displays the hold butterfly curves of the considered SRAM cells in this study at VDD = 0.2 V. Moreover, Fig. 3 exhibits the HSNM variations of all the tested SRAM cells against linear variations in the VDD. It is observed from Fig. 3 that the HSNM value increases with the VDD increment. SRAM cells including the conventional 6T, conventional 8T, and FC11T employ conventional cell core formed by cross-coupled normal inverters pair, and therefore show the same and lower HSNM compared to ST2, ST11T, and ST12T SRAM cells. Although, the PPN10 SRAM cell also uses a conventional cell core, however, it offers the lowest HSNM among all the studied SRAM cells as it has stacked pull-up structure. The ST2 SRAM cell employing modified Schmitt-Trigger inverter-based cell core uses stacked pull-down structure and thus, it has the second-best HSNM. Due to the use of a strong cell core consisting of two Schmitt-Trigger inverters, the ST11T and ST12T SRAM cells has equal and highest HSNM compared to all the SRAM cells at all supply voltages.
3.1.2. Read Stability
The read stability of an SRAM cell is estimated by the read static noise margin (RSNM). The maximum DC noise voltage which an SRAM cell can sustain without changing the data during the read mode is defined as Read Stability (He, 2019). The RSNM is considered as the length of a side of the largest square which is embedded inside the smaller eye of the butterfly curve during the read mode (Gholipour A. a., 2020). Figs. 4 and 5 show the read butterfly curves at VDD = 0.2 V and the RSNM variations versus VDD variations, respectively. The conventional 6T, ST2, and ST12T SRAM cells suffer from the read disturbance issue, resulting in RSNM degradation. These SRAM cells show the lowest RSNM in comparison to other considered SRAM cells at all VDD values. However, the ST2 and ST12T SRAM cells show considerably higher RSNM in comparison to conventional 6T SRAM cell due to their Schmitt-Trigger-based inverters. Other remaining SRAM cells such as the conventional 8T, PPN10T, FC11T, and ST11T employ the read decoupling technique in which data storing nodes are fully isolated from the bitlines during the read operation, results into same values for RSNM & HSNM. The ST11T SRAM cell displays the maximum RSNM amongst all the SRAM cells due to its strong cell core formed by cross-coupled Schmitt-Trigger-based inverters pair.
3.1.3. Writability
Writability of an SRAM cell is determined by the write static noise margin (WSNM), which is the capability of that SRAM cell to pull-down/up a ‘1’/‘0’ storage node to a voltage lower/higher than the switching threshold (Vth) of the another inverter ‘0’/‘1’ storing node; consequently, the state of the cell is successfully flipped (Gholipour E. A., 2020). To calculate the WSNM of an SRAM cell, first, the read VTC of that SRAM cell is combined with its write VTC, and then the length side of the smallest square that can be inserted between and lower half of these VTCs gives the WSNM of the corresponding SRAM cell. Fig. 6 shows the combined read and write VTCs of the studied SRAM cells at VDD = 0.2 V. Furthermore, the WSNM variations of the SRAM cells versus VDD variations given in Fig. 7. As VDD increases, the WSNM values also increase. SRAM cells such as FC11T, ST11T, and ST12T use feedback-cutting, power-gated, and floating virtual ground write-assist techniques, respectively to improve the WSNM. The conventional 8T and PPN10T SRAM cells show lower WSNM to the 6T SRAM cell due to their read VTC. In the ST2 SRAM cell, read access transistors also help to write a ‘0’ or ‘1’ into the cell, resulting in WSNM improvement.
3.2 Access Time or Delay
Access time or delay average of the low-to-high propagation delay (tPLH) and the high-to-low propagation delay (tPHL). These are two kinds of read and write access time (Sanvale, 2019). Table 3 reports the read and write access times of the considered SRAM cells in this study.
Table 3. The speed performance of the various SRAM cells at VDD= 0.2 V.
Speed performance
|
6T
|
8T
|
ST2
|
PPN10T
|
FC11T
|
ST11T
|
ST12T
|
Read Delay (ns)
|
2.75
|
3.64
|
5.63
|
3.64
|
4.91
|
3.64
|
4.21
|
Write Delay (ns)
|
0.30
|
0.30
|
0.38
|
0.39
|
2.38
|
1.67
|
0.74
|
3.2.1. Read Access Time or Read Delay
The reading speed of an SRAM cell is gauged by the read delay or access time (TRA). It is defined as the time between the word line activation when the bit line voltage is discharged by 50 mV from the original high value (Golipour, 2021) (S. Ahmad, 2017). Fig. 8 sows the comparisons of the TRA of the various SRAM cell at different VDD values. From this figure, the 6T SRAM cell demonstrates the lowest TRA due to its reading path, which includes the strong pull-down transistor with an N = 2. Various SRAM cell like the conventional 8T, PPN10T, and ST11T employ the same isolated read path made by two access transistors. Therefore, these SRAM cells show higher TRA in comparison to 6T SRAM cell. In the ST12T SRAM cell, the read path is created by three series-connected access transistors; consequently, this SRAM cell offers higher TRA as compared to the above-mentioned SRAM cells. Because of higher overall bit lines capacitance as a direct consequence of the connection of several access transistors to the same bit lines, the ST2 SRAM cell shows the highest TRA among all the SRAM cells at all VDD values.
3.2.2. Write Access Time or Write Delay
The swiftness of an SRAM cell during the write operation is measured by write access time or write delay (TWA). The TWA is well-defined as the time duration between the word line activation and the time when the storage node Q (QB) reaches 10% (90%) of VDD. The TWA for writing '1' into '0' storing node Q in all the SRAM cells against VDD variations is shown in Fig. 9. The conventional 6T and 8T SRAM cells have the same simple differential writing structure formed by a single access transistor. Therefore, these SRAM cells show the same lowest TWA compared to all the SRAM cells. The FC11T and ST12T SRAM cells show the highest TWA among all the compared SRAM cells due to their single-ended writing operation. However, the FC11T SRAM cell offers higher TWA than ST11T SRAM cell because in the former cell the utilized feedback-cutting write-assist technique changes the cell core to be as two cascaded inverters during the write operation in which one inverter is followed by other one, resulting in TWA increment. In the ST12T SRAM cell, the switching threshold (Vth) of Schmitt-Trigger inverters in the cell core is higher than the normal one. This issue increases the TWA. The SRAM cells including ST2 and PPN10T SRAM cells show almost equally lower TWA than the conventional 6T SRAM cell.
3.3. Dynamic/Leakage Power Consumption
Dynamic/Leakage power consumption of an SRAM cell is the power consumption of the cell when it is accessed/it is in idle mode. Table 4 reports the power consumption of numerous SRAM cells at VDD = 0.2 V.
Table 4. Power consumption of the various SRAM cells at VDD= 0.2 V.
Power consumption
|
6T
|
8T
|
ST2
|
PPN10T
|
FC11T
|
ST11T
|
ST12T
|
Dynamic Power (μW)
|
12.335
|
13.354
|
19.794
|
10.057
|
7.761
|
3.335
|
6.248
|
Leakage Power (nW)
|
0.730
|
0.812
|
0.565
|
0.693
|
0.236
|
0.565
|
0.151
|
3.3.1. Dynamic Power Consumption
Dynamic power (PDyn) is the notable portion of the overall power consumed by an SRAM cell. Since the write power is dynamic power, hence dynamic power expression is used for the calculation of write power. The write power of an SRAM cell is thus given by Eq. (3):
![](https://myfiles.space/user_files/83400_b9e2661d18ef2d4b/83400_custom_files/img1629300792.png)
where α𝑤𝑟𝑖𝑡𝑒 is the switching activity factor, 𝑓𝑤𝑟𝑖𝑡𝑒 is writing frequency. The maximum value for Write activity factor is considered as 1 (Roy, 2020). The Simulation results of write power is shown graphically in Fig. 10. SRAM cells such as the conventional 6T, 8T, ST2, PNN10T, and ST12T employ fully differential writing structure, and therefore their PDyn is higher than other SRAM cells with single-ended writing structure. The ST2 SRAM cell consumes the highest PDyn among all the SRAM cells due to its higher overall bit line capacitances because of the connection of several access transistors to the same bit lines. Although, the FC11T SRAM cell uses a single-bit line for performing both read and write operations, however, its bit line needs to be discharged to the ground for every write operation, and therefore it consumes higher PDyn. The PPN10T and ST12T SRAM cells show lower PDyn than the conventional 6T SRAM cell due to their lower 𝑓𝑤𝑟𝑖𝑡𝑒. In comparison to all SRAM cells, the ST11T SRAM cell offers the least PDyn as it has single-ended nature and lower 𝑓𝑤𝑟𝑖𝑡𝑒.
3.3.2. Leakage Power Dissipation
The leakage power (PLeak) is the power strained by MOS devices from VDD when the cell lies in the standby mode. As an SRAM cell stays maximum of the time in hold mode, therefore the PLeak is an important factor to total power consumption (Golipour, 2021). Fig. 11 compares the PLeak of the various SRAM cells at different VDD values. The conventional 8T SRAM cell displays a higher PLeak to the conventional 6T SRAM cell due to its higher count of bit lines used. Furthermore, this SRAM cell has high leakage in its isolated read path, which becomes significant with technology scaling (S. Ahmad, 2017). The ST2 and PPN10T SRAM cells dissipate lower PLeak than the conventional 6T SRAM cell as stacked transistors are used in their cell core. Although, the ST11T is single-ended and uses stacked transistors, however, this memory cell employs the isolated read path as the 8T SRAM cell, therefore, suffering from isolated read path's leakage. This SRAM cell displays higher PLeak in comparison to FC11T and ST12T SRAM cells.
3.4. Layout Area
The layouts of the considered SRAM cells in this study, created on the design rules for the FinFET technology given in
(Salahuddin, 2013)
, are demonstrated in Fig. 12. The area for each cell is described in Table 5, where λ is the minimum feature size which is considered as 1/2 of the gate length (Ansari, 2015). The conventional 6T SRAM cell displays the minimum layout area because of its simple structure with a minimum count of transistors used among all the considered SRAM cells in this article, the ST12T SRAM cell, on the other hand, consumes the highest layout area, which is attributed to its higher count of transistors utilized in this design.
Table 5. The layout dimensions of the compared SRAM cells are based on λ.
![](https://myfiles.space/user_files/83400_b9e2661d18ef2d4b/83400_custom_files/img1629301452.png)
3.5. Electrical Quality Metric
For comprehensive evaluation of the performance of an SRAM cell, an electrical quality metric (EQM) has been proposed in (Jiao, 2016) and expressed as Eq. (4) to assess the overall excellence of a cell.
![](https://myfiles.space/user_files/83400_b9e2661d18ef2d4b/83400_custom_files/img1629301291.png)
Where, HSNM, RSNM, and WSNM are the static noise margin during the hold, read, and write operations, respectively. TRA (TWA) is the read (write) access time. PDyn is the dynamic write power consumption, PLeak is the leakage power dissipation, and Area is the layout area. It is observed from Fig. 13, which shows the EQM of all cells at VDD = 0.2 V, that the ST12T/ST2 SRAM cell offers the highest/lowest EQM amid all the considered SRAM cells.