In this paper, a novel nanotube tunneling field-effect transistor (NT-TFET) with bias-induced electron-hole bilayer (EHBNT-TFET) is proposed for the first time. By the intentional misalignment and an asymmetric bias configuration of the inner-gate and outer-gate, the line tunneling takes place inside the channel, significantly improving the tunneling rate and area. The device principle and performance are investigated by calibrated 3-D TCAD simulations. Compared to the conventional NT-TFET, the proposed EHBNT-TFET exhibits an increased ON-state current (ION) about 57.2 times and a sub-60 mV/dec subthreshold swing for seven orders of magnitude of drain current. Furthermore, the increased ION and reduced gate capacitance achieve improved dynamic performance. Compared with conventional NT-TFET, the intrinsic delay decreased about 142 times is obtained in EHBNT-TFET.
Research Article
Design Optimization of Nanotube Tunnel Field-Effect Transistor with Bias-Induced Electron-Hole Bilayer
https://doi.org/10.21203/rs.3.rs-869222/v1
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Band-to-band tunneling
nanotube
electron-hole bilayer
line tunneling
steep switching
As feature size scales down constantly, conventional MOSFETs have reached physical limitation. Power dissipation rises considerably due to the high-leakage current and unscalable supply voltage (VDD) [1]. With the rising demand for mobile phones, lower power is becoming an important requirement and some novel devices have been proposed, such as negative capacitance field-effect transistor, impact ionization metal-oxide-semiconductor transistor and tunnel field-effect transistor [2–7]. The quantum tunneling in tunnel field-effect transistor (TFET) achieves an extremely-low OFF-state current (IOFF) and a steep subthreshold slope (SS) below 60mV/dec at room temperature [7], so that VDD could be further scaled down.
However, two major challenges restrict TFET in practical applications. The first one is the difficulty of achieving the highly doped source/channel junction with ultra-steep profile experimentally [8]. Though dopingless TFET provides a solution to avoid the high-temperature doping/annealing processes [9], the ON-state current (ION) degrades due to the existence of large barrier width between source and gate electrodes [10]. The second one is low ION, caused by poor band-to-band tunneling rate and the point tunneling mechanism. To improve ION of TFET, several approaches have been proposed, such as low bandgap material engineering [11–12], high-k gate dielectric engineering [13], source pocket engineering [14–15] and line tunneling engineering [16–20]. Bias-induced electron-hole bilayer (EHB) concept was applied to double-gate TFET to induce line tunneling in the channel [17–19]. However, 2-D planar structure is difficult to achieve large ION with small chip-area [20]. Besides, nanowire TFET (NW-TFET) also presents a great potential for performance enhancement because of the excellent electrostatic control. However, dynamic performance and power dissipation of NW-TFET are bound to be affected, when multiple nanowires are vertically stacked to increase the tunneling area. Compared to NW-TFET, nanotube TFET (NT-TFET) achieves similar electrostatic control by the inner/outer-gate, and offers larger tunneling area and current by hollowed cylindrical shaped nanotube structure [21–24]. However, NT-TFET still suffers from the two challenges mentioned above.
In this paper, a novel NT-TFET with a misaligned inner/outer-gate, named EHBNT-TFET, is proposed for the first time. With appropriate gate work-function and bias configuration, electron-hole bilayer is induced separately, forming an abrupt p+-n+ junction in the intrinsic channel. As a result, the highly doped source/channel junction with abrupt profile is not required in EHBNT-TFET. Using 3-D device simulation, the advantage of EHBNT-TFET is explored and demonstrated in detail. The line tunneling inside the channel dominants the current, instead of the point tunneling between source and channel. Compared to the conventional NT-TFET, ION of EHBNT-TFET is found to increase about 57.2 times and keep a high ION/IOFF ratio of 1.94×109. Furthermore, the impact of doping concentration, critical geometric parameters, gate work-function and bias are discussed, which benefits to adopt appropriate parameters to achieve excellent performance.
3-D schematic view of conventional NT-TFET and proposed EHBNT-TFET are shown in Fig. 1(a) and (b), respectively, and the corresponding cross-sectional view along A-A' cut-plane are presented in Fig. 1(c) and (d). Conventional NT-TFET has a symmetric inner/outer-gate with the same metal work-function, and generally the same bias is applied to the inner/outer-gate. The EHBNT-TFET presents an intentional misaligned inner/outer-gate. The inner-gate has a higher work-function, compared to the outer-gate. When a positive voltage is applied to the outer-gate and a negative voltage is applied to the inner-gate, a bias-induced electron-hole bilayeris formed in the thin silicon nanotube channel. Consequently, an abrupt p+-n+ junction is formed in the intrinsic channel. Then the line tunneling occurs between electron-hole bilayer, i.e., the overlapped region between the inner-gate and outer-gate. Furthermore, the underlap at the source and drain end could eliminate parasitic tunneling current in OFF-state. Referring to the fabrication of previous NT-TFET [24-27], a possible process flow for proposed EHBNT-TFET is presented in Fig. 2. The main difference in EHBNT-TFET is the formation of misaligned inner/outer-gate using different materials.
The simulations are performed using Sentaurus TCAD [28]. Besides the regular physical models, dynamic nonlocal path band-to-band tunneling (BTBT) and density gradient (DG) model are also activated. Dynamic BTBT adopts Wentzel-Kramers-Brillouin (WKB) approach to account for phonon-assisted tunneling process [29]. DG model is used to consider the quantum confinement effect. For the moment, trap-assisted tunneling process has not been considered in our simulations. The simulation environment is calibrated with the previous result of conventional NT-TFET under the same geometric parameters [24]. As shown in Fig. 3(a), the simulated transfer curve shows a good agreement with the data in [24]. For tunneling occurring at electron-hole bilayer, the correct computation of carrier density is critical. Therefore, DG model has been calibrated on the solution of the Poisson-Schrödinger equation with the structure in Fig. 1(c). Calibrated DG model parameters are given as follows: γn = 7, γp = 10.5, ηn = 1.02, ηp = 0.8, θn = 0.91, θp = 0.97. As shown in Fig. 3(b), charge distributions in the channel arising from calibrated density gradient model matches properly with Schrödinger results for EHBNT-TFET.
The key physical parameters of simulated NT-TFET and EHBNT-TFET are listed in Table 1. The intrinsic Si is adopted as the channel. To keep the same geometry, gate length of NT-TFET is 40 nm, while the overlap between inner/outer-gateof EHBNT-TFET is 20 nm, with a 10 nm underlap between inner-gate (outer-gate) and drain (source). The work-function of NT-TFET is tuned to obtain the same IOFF with EHBNT-TFET. By default, the applied voltage VDD is 0.5 V.
3.1 Characteristics of NT-TFET and EHBNT-TFET
Transfer characteristics for both NT-TFET and EHBNT- TFET are depicted in Fig. 4(a). For EHBNT-TFET, the outer-gate controls the switch between OFF-state and ON-state. Compared to the conventional NT-TFET, EHBNT-TFET offers an increased ION by 57.2 times without any IOFF degradation. Here, IOFF is defined as drain current when the outer-gate bias (VOG) is 0 V and inner-gate bias (VIG) is -0.1 V. ION is defined as drain current when VOG is VDD with fixed VIG of -0.1 V. Besides, proposed EHBNT-TFET presents a significant improvement in terms of drain current and subthreshold slope (SS), exhibiting a sub-60 mV/dec SS for seven orders of magnitude of drain current, as shown in Fig. 4(b). Furthermore, the minimum SS in EHBNT-TFET is 2.1 mV/dec, while it is 28.5 mV/dec in NT-TFET. The steep OFF/ON switch offers a reduced SS which proves the excellent gate control in EHBNT-TFET.
In TFET devices, ION is governed by the inter-band tunneling current across tunneling barrier. With WKB approximation, the tunneling current is calculated as [30]
$${I_{BTBT}} \propto A{e^{( - \frac{{4 \times \sqrt {2{m^}} \times {E_g}^{{3/2}}}}{{3q\hbar E}})}}$$ 1 Where m
To evaluate the physical mechanism further, the energy band diagrams of two transistors along B-B' (parallel to channel) and C-C' (perpendicular to channel) cut-line are shown in Fig. 5(a)~(d). For EHBNT-TFET, there is no overlap between the conduction band and valence band of channel in OFF-state, no matter along channel or perpendicular to channel, as shown in Fig. 5(a) and (b). As VOG increases, the energy band bends downward and energy overlap appears. The tunneling distance along C-C' cut-line is much shorter than that along B-B' cut-line. Therefore, the line tunneling dominates in EHBNT-TFET, and the lateral point tunneling from source to channel is negligible. On the contrary, as demonstrated in Fig. 5(c) and (d), only point tunneling along the source/channel interface exits in NT-TFET. Due to the limited silicon channel thickness, the line tunneling distance in EHBNT-TFET is greatly lower than the point tunneling distance in NT-TFET, as presented in Fig. 5(e). Furthermore, the line tunneling distance decreases with VOG increasing. The total tunneling strength in both devices is depicted in Fig. 5(f) as a function of gate voltage. It is the smaller tunneling distance that results in the improvement of tunneling rate. The short tunneling distance and large tunneling rate contribute to the improved tunneling strength in EHBNT-TFET.
The dynamic performance of NT-TFET and EHBNT-TFET is compared in Table 2. The intrinsic delay time τ is calculated as Cgg×VDD/ION [
31], where Cgg is the extracted gate capacitance. Cgg of EHBNT-TFET is lower than that of NT-TFET by 59% due to the existence of underlap between inner-gate (outer-gate) and drain (source). Furthermore, intrinsic delay time τ of EHBNT-TFET is reduced about 142 times, due to the combined result of decreased Cgg and improved ION.
The transfer characteristics of EHBNT-TFET under various supply voltage is depicted in Fig. 6(a). The extracted transition voltage (VTR) keeps constant while IONdeclines as VDSdecreases from 0.5 V to 0.1 V, as shown in Fig. 6(b). VTR is defined as the outer-gate voltage where the line tunneling starts, and SS has the minimum value [17]. As the outer-gate voltage increases to VTR, electrons start to tunnel from the valence band of induced p+ layer to the conduction band of induced n+ layer in channel. Here the line tunneling in EHBNT-TFET is dominated by gate electric field, while is not affected by drain voltage. Therefore, a constant VTR is expected as VDS increases. A lower VTR could allow a lower supply voltage.
3.2 Impact of doping in EHBNT-TFET
The impact of drain doping (ND) on EHBNT-TFET under various underlap between inner-gate and drain (LIGUD) is depicted in Fig. 7, where source doping (NS) is fixed at 5×1019 cm-3 and underlap between outer-gate and source (LOGUS) is fixed at 10 nm. IOFF remains nearly unchanged for lower ND, while it begins to increase once ND exceeds 1×1018 cm-3, and the increasing trend is weakened as LIGUD increases, as depicted in Fig. 7(a). ION monotonically increases as ND increases for a small LIGUD, while it keeps nearly unchanged once LIGUD exceeds 6nm, as depicted Fig. 7(b). Furthermore, a larger LIGUD presents an improved ION. In EHBNT-TFET, IOFF is comprised of SRH recombination as well as parasitic tunneling from drain to induced p+ layer.As ND increases, the carrier lifetime declines and then SRH recombination increases. As shown in Fig. 8(a), SRH recombination dominates IOFF under lower ND, and the parasitic tunneling dominates IOFFunder high ND. The sharply increased IOFFunder ND of 1×1019 cm-3 is the result of increased parasitic tunneling.As demonstrated in Fig. 8(b), there is no band overlap between drain and channel under low ND. However, when ND rises to 1×1019 cm-3, the energy band has overlap and the tunneling distance between drain and channel is enough thin, leading to an increased parasitic tunneling current. As shown in Fig. 8(c), the tunneling distance between drain/channel junction increases under larger LIGUD. Thus,ND has less impact on IOFF with LIGUD increasing. The trend of ION could be illustrated by Fig. 8(d), taking the case of LIGUD = 2 nm as an example. For a smaller ND, the high barrier between channel and drain leads to a low ION. With ND increasing, the energy band in drainbends downward, resulting a lower barrier and then a higher ION. The effect of larger LIGUD is similar to that of high ND.Furthermore, the impact of ND on barrier is weakened for a larger LIGUD, so that ION is barely affected. It is observed that the proposed device achieves better dc performance at LIGUD = 10 nm and ND = 1×1018 cm-3.
Fig. 9 depicts the impact of NSunder various LOGUS, where ND is fixed at 1×1018 cm-3 and LIGUD is fixed at 10 nm. As shown in Fig. 9(a). WhenNS is lower than 1×1019 cm-3, IOFF remains unchanged for arbitrary LOGUS. As NS further increase, IOFF gradually increase especially for the smaller LOGUS, such as 2 nm and 4 nm. ION increases with NS increasing especially forsmaller LOGUS, as shown in Fig. 9(b). Here the parasitic tunneling between drain and channel could be ignored due to the large LIGUD and low ND. As shown in Fig. 10(a), SRH recombination keeps constant and therefore BTBT from source to channel dominates the trend with NS. As NS rises up to 5×1019 cm-3, particularly for LOGUS = 2 nm, electron begins to tunnel from source to channel. The larger IOFF under NS of 1×1020 cm-3 is the result of energy band overlap between source and channel in OFF-state. Due to low work-function of the outer-gate, the increased NS leads to a declined tunneling distance and an improved tunneling rate from source to channel under low LOGUS, as represented in Fig. 10(b). Thus, the parasitic tunneling between source and channel increases and dominants IOFF under low LOGUS and high NS, leading to a large IOFF. However, with LOGUS increasing, tunneling between source and channel hardly takes place due to large tunneling distance. The increased trend of ION is because high NS could provide more hole in induced p+ layer. Similarly, the impact of NS is weakened by larger LOGUS. Considering the tradeoff between IOFF and ION, LOGUS = 10 nm is recommended as the most suitable geometry. Meanwhile, lower NS could be adopted and the requirement of extremely steep doping profiles between source and channel is not necessary for EHBNT-TFET.
In conventional TFET IOFF is mainly affected by ND and ION is only sensitive to NS [
31]. However, in EHBNT-TFET ION is dominated by the line tunneling in channel, and the large underlap at source and drain end eliminate the effect of ND/NS on IOFF. Therefore, ND and NS have little impact on device performance of EHBNT-TFET with large LIGUD and LOGUS.
3.3 Impact of geometric parameters in EHBNT-TFET
The effect of overlap between inner/outer-gate (LIOGO) and inner-gate diameter (DIG) are shown in Fig. 11. ION and ION/IOFF gradually improves with LIOGO and DIG increasing, due to the increased line tunneling area. Although the increased LIOGO and DIG also leads to a degraded IOFF, ION has greater improvement than IOFF so that ION/IOFF is improved. The EHBNT-TFET provides much higher scalability with the help of circular cylinder channel. Compared with EHBTFET, tunneling area can be extended with smaller device size by larger DIG for EHBNT-TFET. Larger LIOGO can achieve higher current drivability without any integration density loss. Furthermore, the proposed EHBNT-TFET shows much higher normalized ION and ION/IOFF than conventional EHBTFET due to better gate control, as shown in Table 3.
As shown in Fig. 13, the extracted VTR decreases, i.e., the line tunneling starts at lower VOGwith TSC increasing. The energy band perpendicular to channel inOFF-state is presented in Fig. 13(b). No overlap exists between the conduction band and valence band when TSC increases from 3.5 nm to 5.5 nm. The conduction band near outer-gate is 0.189 eV higher than the valence band near inner-gate at TSC = 3.5 nm, while it is only 0.011 eV at TSC = 5.5 nm. Therefore, a larger VOGisrequired at TSC = 3.5 nm to pull down the energy band to create the line tunneling in channel, compared to the case of TSC = 5.5 nm. As a result, a higher VTR is obtained for smaller TSC. According to the analysis above, a TSC of 4 nm could be adopted to improve dc performance of EHBNT-TFET.
3.4 Impact of gate work-function and inner-gate bias in EHBNT-TFET
The effect of work-function of outer-gate (ФOG) is shown in Fig. 14. IOFF and ION increases monotonously, while VTR decreases as ФOG decreases from 3.95 eV to 3.75 eV. The lower ФOG causes more inverse electron in the channel, leading to a higher SRH recombination rate and an increased IOFF. As ФOG decreases, the energy band of channel beneath outer-gate moves downward and a steeper p+-n+ junction is formed, as shown in Fig. 14(c). As a result, an increased ION is observed due to the decreased tunneling distance and increased overlapped energy range. To explore the variation of VTR, the energy band perpendicular to channel in OFF-state is plotted in Fig. 14(d). In the case of ФOG = 3.95 eV, the conduction band near outer-gate is 0.138 eV higher than the valence band near inner-gate, while it is only 0.01 eV at ФOG = 3.75 eV. As a result, a higher ФOG results in a larger VTR.
The impact of work-function of inner-gate (ФIG) is shown in Fig. 15. In contrast to the case of ФOG, IOFF and ION increases monotonously, while VTR decreases as ФIG increases from 5.25 eV to 5.45 eV. The increased ФIG have the similar effect on device performance with decreased ФOG. More carrier in the channel due to increased ФIG leads to an increased IOFF. Similarly, by decreasing surface potential of the channel near inner-gate, the energy band of channel beneath inner-gate is pulled upward, as shown in Fig. 15(c), resulting in an increased ION. As for transition voltage VTR, the energy band perpendicular to channel inOFF-state is plotted in Fig. 15(d). In the case of ФIG = 5.25 eV, the conduction band near outer-gate is 0.136 eV higher than the valence band near inner-gate, while it is only 0.013 eV at ФIG = 5.45 eV, leading to a lower VTR at high ФIG. In short, thecharacteristics improve with increasing ФIG.
The effect of ФIG and VIG on EHBNT-TFET is compared by design of experiment in Table 4. It is found that transfer characteristics of experiment No. 1 is exactly the same with that of experiment No. 3, experiment No. 2 and No. 4 is also the same. In short, the reduction of ФIG have the same effect on device performance with increased VIG. The same effect of ФIG and VIG makes it more flexible for device and circuit design.
In this paper, a novel NT-TFET with an intentional misaligned inner/outer-gate has been proposed, achieving excellent static and dynamic performance. Line tunneling between electron-hole bilayer offers the steep transition from OFF-state to ON-state and high drive current. ION is found to improve by 57.2 times, and a sub-60mV/dec subthreshold slope for seven orders of magnitude of drain current is obtained. In addition, the impact of doping on static performance was discussed in detail. The performance of EHBNT-TFET is almost unaffected by source and drain doping with large underlap. The immunity of doping eliminates the requirement for formation of abrupt source/channel junction and high thermal budget in fabrication process. Meanwhile, the characteristics of various geometric parameters was studied to obtain better device performance. Due to the electron-hole bilayer induced by appropriate gate configuration, gate work-function and bias are significantly important to offer superior performance.
Acknowledgments The authors are grateful to National Natural Science Foundation of China, Natural Science Foundation of Shang under Grant, Shanghai Science and Technology Innovation Action Plan and Science and Technology Commission of Shanghai Municipality for the financial support.
Author contributions Conceptualization, methodology, writing- original draft preparation: Xueke Wang; Data analysis: Xueke Wang and Yabin Sun; Writing- review and editing: Yun Liu and Xiaojin Li; Supervision: Ziyu Liu and Yanling Shi; Resources and funding acquisition: Ziyu Liu.
Funding This work was supported in part by National Natural Science Foundation of China under Grant 61974056, in part by Natural Science Foundation of Shang under Grant 19ZR1471300, in part by Shanghai Science and Technology Innovation Action Plan under Grant 19511131900, and in part by Science and Technology Commission of Shanghai Municipality under Grant 14DZ2260800.
Availability of data and material The data and material that support the findings of this study are available on request from the corresponding author.
Code availability Not Applicable.
Competing interest Not Applicable.
Ethics Approval Not applicable.
Consent to Participate Not applicable.
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Disclosure of potential conflicts of interest Authors have no conflicts of interest to declare that are relevant to the content of this article.
Research involving Human Participants and/or Animals Not applicable.
Informed consent Not applicable.
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Table 1 : Device parameters for the simulated NT-TFET and EHBNT-TFET
Table 2: Dynamic performance for the NT-TFET and EHBNT-TFET
Table 3 : Performance comparison of EHBTFET and EHBNT-TFET
Table 4 : Experiments with different inner-gate work-function and bias for EHBNT-TFET
