Another substitute for the planar CMOS structure is the FinFET non-planar structure. "This structure forms a double gate where the gate is placed on two, three, or four sides of the channel" (Cha et al., 2005; B. H. Calhoun & A. Chandrakasan et al., 2007). Hence, FinFET devices are called multi-gate FinFET. The term ‘fin’ is called the raised channel as shown in Fig. 2.
FinFET technology is used to overcome the SCEs for the realization of the cell, and it is convenient to downsize underneath sub 32nm nodes. This paper depicts the use of a double-gate (DG) FinFET 6T cell, compared with a conventional CMOS 6T cell. It has a significant improvement in leakage power consumption, and it examines the 6T cell design using SG Double Gate or Tied-Gate FinFET with parameters of Fin height (Hfin), gate length (Lg), and Fin thickness (Tsi), which are tabulated in Table 3 (A. Islam & Mohd. Hasan, et al., 2012; Y.Wei et al., 2014).
The circuit used for the FinFET 6T cell is equivalent to the CMOS 6T cell represented in Fig. 2 except that the gate structure used here is non-planar (as shown in Fig. 1). The number of fins selected for pull-up, pull-down, and gate transistors is shown in Table 3. "Under a given contact size, the maximum number of fins (Nfin) is determined by the fin thickness (Tfin) and the fin-to-fin spacing". "A fin thickness of 10-20nm is the typical range for implementing strong electrostatic control in the double-gate scheme to reduce SCEs" (Son et al., 2011; PTM. 2012). The characteristics of 6T cells are obtained from HSPICE simulations of the low standby power (LSTP) FinFET under sub-32nm technologies are compared and studied. In each technology node, design considerations shown in Table 4 must be followed. Read, write, and hold are the three basic functions of a FinFET 6T SRAM cell.
3.1 Hold operation:
The ground is attached to the word line (WL). M5 and M6 are switched off as a result, isolating the latching component from two bit lines. As a result, M1, M2, M3, and M4 created a latching architecture that held a preserved data bit as longer as the bit-lines were unconnected.
3.2 Read operation:
Bit-lies are already charged to VDD in this procedure, and the WL is likewise attached to VDD. Transistors M5 and M6 are turned on in this condition. M1 and M4 are turned off, and M3 and M2 are turned on, according to data circumstances Q = ‘‘1" and Qbar = ‘‘0". As a result, BLB-M6-M2 will carry bit-line current. As a result, the voltage degree of the bit-line BLB drains, while the voltage degree of the BL remains at VDD.
3.3 Write operation:
The bit-lines' voltage levels are polar opposites, and the WL is coupled to VDD. The transistors M5 and M6 will be turned on as a result of this. Here, the voltage degree of node Q declines while the voltage degree of node Q' increases till the voltage degree of Q is sufficient to turn on M4 while turning off M2 or the voltage degree of node Q' is adequate to switch on M3 while turning off M1. The voltage levels of Q' and Q shall then be changed to ‘1' and ‘0,' correspondingly.
Table 3
Transistor ratio of FINFET 6T cell design
Transistors
|
No of fins (Nfin)
|
Pull-up M2, M4
|
1
|
Pull-down M1, M3
|
3
|
Access M5, M6
|
2
|
Table 4
HSPICE simulation parameters of FinFET 6T cell
Parameters
|
16nm
|
20nm
|
22nm
|
Lg (nm)
|
20
|
24
|
25
|
Tsi (nm)
|
12
|
15
|
12
|
Hfin(nm)
|
26
|
28
|
40
|
Supply voltage (V)
|
0.85
|
0.9
|
0.95
|