The modern technology aims for rapid communication devices that can surpass the diffraction limit of photonic devices, and plasmonics have shown to be a viable option in this regard [1–3]. It is the science that focuses on generating, optical signal detecting and processing at metal-dielectric interface [4]. Plasmonic waveguides may be used to address the main disadvantages in a plasmonic circuit, such as restricted propagation time, rise in temperature and difficulty in changing the signal direction. In recent years, researchers have examined different plasmonic waveguides including MIM, IMI, and dielectric-loaded surface plasmon polaritons (DLSPP) [5]. Compared to insulating waveguides, plasmonic MIM waveguides enable greater confinement and therefore been presented as a potential option for nanoscale optical circuits [6–10]. Logic gates are essential components in all optical circuit design and a numerous optical equipments, like directional coupler (DC), Mach–Zehnder interferometer (MZI), power couplers, and power dividers, are utilized to realise logic gates such as AND, OR, NOT, XOR, and XNOR, along with universal gates such as NAND and NOR [11]. As a result, these all-OLGs may be utilised to construct any combinational circuit, including multiplexers, de-multiplexers, parity generator, adders and subtractors, and code translators [12–15]. Conventional OLGs give cut-off states and interferometric effects, but plasmonic logic gates greatly minimise size and signal losses; it can also lower signal thresholds of logic operations and offer rapid switching in optical devices.
The framework of the suggested paper presents a simplified all-optical NAND gate design with power coupling concept employing a Y waveguide and simulated in FDTD software. The Y-power coupler plasmonic NAND gate design is reported in Sect. 2. Section 3 presents the simulation findings. Section 4 has a results analysis, in which the current study is also compared to prior published studies, and Sect. 5 concludes the paper.
2. The all-optical plasmonic NAND gate structure employing Y-power combiner
A miniaturized all-optical plasmonic NAND gate is modelled by arranging S-bend and linear waveguides of equal width (W) using power combiner concept. The presented design is obtained in a wafer size of 6.2 µm × 3 µm by arranging two parallel S-bend waveguides of equal length (Ls) along XZ axis in Y shape separated by a distance (D) and joined to single end of a linear waveguide of length (L) whose structure is shown in Fig. 1. An external change in the phase controls the inputs supplied to both ends of the power combiner. The final minimised structure is achieved by varying the Y-combiner parameters such as the Ls, D, and L.
By altering the length of S-bend waveguide (Ls) and maintaining the separation gap between inputs (D) as 2.5 µm, different factors like the highest output power when turned ON and OFF and also ER may be determined, as shown in Table 1. It is observed that for S-bend length of 3.6 µm, the obtained ER value is 27.76 dB that is higher compared to the rest. The S-bend length versus ER plot is depicted in Fig. 2.
Table 1
ER for different values of S-bend length (Ls) in Y-shaped plasmonic NAND gate
Sl. No. | S-bend length (µm) | PON | POFF | Extinction ratio (dB) |
1 | 3.1 | 4.26 | 0.009 | 26.75 |
2 | 3.2 | 4. 31 | 0.008 | 27.31 |
3 | 3.3 | 4. 36 | 0.008 | 27.36 |
4 | 3.4 | 4. 37 | 0.008 | 27.37 |
5 | 3.5 | 4. 32 | 0.008 | 27.32 |
6 | 3.6 | 4.18 | 0.007 | 27.76 |
7 | 3.7 | 4.28 | 0.011 | 25.90 |
Similarly, all parameters indicated are indeed computed by changing the value of D by maintaining Ls at 3.6 µm, the results are tabulated in Table 2. It is observed that ER is more for a separation between waveguide of 2.6 µm resulting in 27.76 dB. The separation between waveguides versus ER is plotted and displayed in Fig. 3.
Table 2
ER for various separations between S-bend waveguides (D) of the Y shaped plasmonic NAND gate power combiner
Sl. No. | D | PON | POFF | Extinction ratio (dB) |
1 | 2.6 | 4.18 | 0.007 | 27.76 |
2 | 2.7 | 4. 40 | 0.01 | 26.43 |
3 | 2.8 | 4. 46 | 0.01 | 26.49 |
4 | 2.9 | 4. 46 | 0.01 | 26.49 |
5 | 3.0 | 4. 41 | 0.01 | 26.44 |
The length of S-bend waveguide and D are maintained constant at 3.6 µm and 2.6 µm, correspondingly, whereas the linear length of waveguide is adjusted to get the highest ER. Table 3 presents the ER for various linear lengths of waveguide. The higher ER of 26.87 dB is reported for L = 2.5 µm. A linear length waveguide versus ER plot is depicted in Fig. 4 and the final dimensions of the Y-power coupler plasmonic NAND gate with the highest ER are tabulated in Table 3.
Table 3
ER of different linear waveguide lengths of Y-shaped plasmonic NAND gate
Sl. No. | Linear length | PON | POFF | Extinction ratio (dB) |
1 | 2.4 | 4.32 | 0.009 | 26.81 |
2 | 2.5 | 4. 38 | 0.009 | 26.87 |
3 | 2.6 | 4. 36 | 0.009 | 26.85 |
4 | 2.7 | 4. 31 | 0.009 | 26.80 |
5 | 2.8 | 4. 29 | 0.009 | 26.78 |
6 | 2.9 | 4.35 | 0.009 | 26.84 |
The structural requirements obtained by altering dimensions of the presented Y- power combiner plasmonic NAND gate design are tabulated in Table 4.
Table 4
The design parameters of plasmonic Y shaped NAND gate
Sl. No. | Parameter | Value |
1 | length of S-bend waveguide(Ls) | 3.6 µm |
2 | Length of linear waveguide (L) | 2.5 µm |
3 | Separation between input waveguides (D) | 2.6 µm |
4 | Refractive index (n) | 2.1 |
5 | Width of the waveguide (W) | 0.25 µm |
3. The Y-power combiner plasmonic NAND gate FDTD simulation results
The optimized all-optical NAND gate design contains plasmonic waveguide of refractive index (n) = 2.1 and continuous-waveform (CW) in transverse electric (TE) mode, with wavelength (λ) of 1.55 µm is provided at both inputs. The power at input is 0.7e9 W/m and 3e9 W/m for low and high intensity optical signals, respectively. The presented structure is analysed using the FDTD technique and Table 5 shows the parameters of the simulation for the design proposed.
Table 5
Simulation parameters of Y-shaped plasmonic NAND gate power combiner
Parameter | Value |
Polarization type | TE |
λ | 1550 nm |
X mesh Size (µm) | 0.0114 |
Z mesh Size (µm) | 0.0114 |
X mesh cells | 349 |
Z mesh cells | 603 |
Transverse Input feld | Gaussian |
Low-intensity power | 0.7 × 109 W/m |
High-intensity power | 3 × 109 W/m |
Figure 5 depicts the propagation of light along the proposed NAND gate for the specified input signal pairings using the FDTD method. When either one or both of the inputs are low, the NAND gate's output is high as shown in the truth Table 6; otherwise, the output is low.
Table 6
The NAND gate’s truth table, as well as the given input phase
Input | Output |
A | B | Phase A | Phase B | (A × B)’ |
0 | 0 | \({0}^{0}\) | \({0}^{0}\) | 1 |
0 | 1 | \({0}^{0}\) | \({0}^{0}\) | 1 |
1 | 0 | \({0}^{0}\) | \({0}^{0}\) | 1 |
1 | 1 | \({180}^{0}\) | \({0}^{0}\) | 0 |