In this proposed work, performance of junctionless transistor with the use of spacers has been evaluated at 15nm gate length in Cogenda TCAD tool. This work is implemented as variation in four parts: changing the spacer extension length, placement of spacers having dual-κ, proportion of low and high-κ spacers, and value of high-κ dielectric constant. Impact of all these parameters is considered on the output of proposed device in terms of various output parameters like on-current (ION), off-current (IOFF), subthreshold swing (SS), drain induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (Vea) and intrinsic gain (Av). From the simulations, it has been observed that placing spacers of dual-κ along the left and right sides of gate region has improved device performance in terms of output parameters. Due to increased gate capacitances, the increase in dielectric constant value has degraded the device performance for longer spacer extension length. However, for shorter spacer extension length, the device characteristics are improved as the value of dielectric constant is increased. Therefore a trade-off is required to get the optimum results of the device.
Research Article
Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15nm gate Length
https://doi.org/10.21203/rs.3.rs-931618/v1
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Junctionless transistor
Dual-κ spacer
Spacer engineering
Subthreshold swing
Short channel effects
CMOS technology has grown tremendously over the past few years. The process of Scaling allows more numbers of components to be accommodated over the given chip area. This growth in number of transistor over an IC was well predicted by Gordon E. Moore in 1965 [1]. Below 20 nm technology, it is difficult to form sharp source and drain junctions in planar MOS transistor. For creating these junctions, doping concentration gradient needs to be high and should be processed at low temperatures. Different structures like Fin shaped FET (FinFET) and Double-gate MOSFET (DG-FET) provides superior immunity against adverse effects occurring at short channel, commonly known as SCEs [2]. More than one gate allows better gate control and lowers drain induced barrier lowering (DIBL) [3]. Junctionless transistor (JLT) was invented by researchers to avoid formation of sharp junctions and cost annealing problems [4]. This kind of structure doesn’t have any junctions between source-channel-drain regions. All these regions have same doping type and concentrations. The JLT can act like a resistor where gate voltage controls the drive current [5]. JLT has advantages of being simple from fabrication point of view and requires low thermal budget [6]. Compared to inversion-mode (IM) FETs, junctionless (JL) FET has more reliability which was demonstrated by Toledano-Luque et al. [7]. Junctionless accumulation mode (JAM) FinFET based on Bulk isolated junctions was demonstrated in 2013 for the first time [8]. This structure has lower cost of substrate than Silicon on insulator (SOI) and was compatible with existing CMOS technology.
The effect of high-κ material as spacer in Junctionless transistor was investigated which showed the improvement in device performance and has lesser short channel effects [9]. Dual-κ spacers are combination of low and high-κ materials acting as spacers. High dielectric spacers are generally used nearer the fin, which lowers the leakage current and hence lesser SCE due to increased fringe field coupling between gate and region of underlap [10].
Dual-κ spacer impact was demonstrated on double gate FET that controls the direct tunneling between source and drain [11]. Dual-κ spacer gives better results than the low-κ spacers in junctionless transistor [12]. Length of spacer and value of dielectric constant (κ) also play significant role in device performance [13].
Different dielectric spacers with different proportion and configurations can be used for better device characteristics as compared to the conventional FET [14–17]. Recently, the significant reduction in power has been examined in performance of JLT has been improved using spacer engineering. Dual-κ spacer length was optimized to improve the subthreshold performance [18]. Impact of Spacer extension length (Lext) and placement of spacers on only drain side, both sides, only source side on Trigate FET was explored by [19] to enhance the analog performance.
Therefore proposed work is aimed at demonstrating the impact of spacer engineering on junctionless transistor design. The whole work has been carried out by varying Lext, dielectric value of high κ spacer, placement and proportion of dual-κ spacers.
This paper has been divided into following sections: Next Section describes the design setup of the proposed device. In Section 3, various simulated results have been discussed and the conclusion of the work is presented in Section 4.
Junctionless device with dual-κ spacer at 15 nm length of gate (Lg) is designed using Cogenda TCAD software. Height of fin (Hfin) is 20 nm and width of fin (Hfin) is also fixed at 20 nm. Tungsten with 4.96eV work function is used for gate terminal. Source region and drain region are doped with concentration of 1×1021 cm-3 while channel doping is 1×1018 cm-3 [20]. Spacer extension length (Lext) is fixed at 1.5 × Lg i.e. 22.5 nm and 2 × Lg i.e. 30 nm respectively. The proportion of high-κ material in dual-κ spacers has been taken as 4:1 (Llk:Lhk) 1:4, 3:2, 2:3 where Llk and Lhk represents the low-κ and high-κ materials respectively [14].
Equivalent oxide thickness (EOT) [21] defined in (1) calculates the values of SiO2 and HfO2 thickness as 0.7 and 3.1 nm resulting in overall value of 1.25 nm. SiO2 has been used as interfacial layer below HfO2.
For dual-κ spacers, SiO2 was used as low-κ material and high-κ material has been changed to 30, 22.3 and 15 respectively. Under-fin doping concentration value is 5×1017 cm-3. Others important design parameters of the designed device are:
Parameter Value
Length of Spacer extension region (Lext) 1.5x, 2x gate length
Dielectric constant of high-κ spacer 15, 22.3, 30
Proportion of low and high-κ spacer 4:1, 1:4, 2:3, 3:2
Placement of spacers with dual dielectrics is aligned in three formats: (i) on source side, (ii) on drain side, and (iii) on both sides.
Fig.1 (a) and Fig. (b) show the 3D picture of designed junctionless transistor with dual-κ spacers on two sides of gate region for different spacer extension length. Fig. 2 (b) shows the internal structure of designed device where fin was covered with EOT.
To check the validation of Cogenda TCAD tool, experimental results obtained by Choi et al. in [20] and simulated results junctionless accumulation mode (JAM) FinFET have been plotted as shown in Fig. 3 which are close in agreement with each other.
ION denoting ‘On current’ and IOFF denoting ‘off current’ are calculated at gate supply voltage of 1 V and 0 V respectively while keeping drain supply fixed at 0.05V. Drain induced barrier lowering current is measured by (Weff /Lg) × 10−7A i.e. 4 × 10−7A at Vd of 20 mV and 1 V respectively. Weff denotes effective channel width and defined in equation (2) [22].
For this case, spacer extension length (Lext) has value of 22.5 nm i.e. 1.5 × Lg as shown in Figure 1(a).
(a) Effect of variation in spacer placement
In this, dual-κ spacers are kept on the side of source, both sides and on the drain side respectively. Dual-κ spacers on drain side resulted in minimum DIBL of 98 mV/V, output conductance (gd) of 9.78× 10-6 S and maximum early voltage (Vea) of 4.02 V due to improved gate fringing coupling towards the drain side for Lext=1.5 × Lg. However, metrics (i) ION/IOFF, (ii) subthreshold swing (SS), (iii) transconductance (gm), (iv) transconductance generation factor (TGF = gm/Id), (v) intrinsic gain (Av = 20 log(gm/gd)) are better for dual-κ (both sides) structure.
(b) Effect of variation in proportion of spacers
Variation in proportion of low- and high-dielectric spacers (4:1, 1:4, 3:2 and 2:3) has been done. From the simulations, it has been concluded that for 2:3 ratio of low and high-κ spacers, almost all parameters of the designed device were improved. But maximum gain of 56.73 dB was observed for 3:2 ratio of dual-κ (both sides) device for κ = 30.
(c) Effect of variation in κ-value of high dielectric material in spacer region
Dielectric value of high-κ material in dual dielectric spacers has been changed to 15, 22.3 and 30. As the κ value of high-κ material is increased, an improvement in performance parameters of device has been observed as shown in Figure 4 to 6.
Table 1 shows the device parameters obtained for dual-κ spacer placement along source, both-sides and drain respectively.
Table 1. Performance parameters of dual spacers on source, both-sides and drain side respectively for κ =15, 22.3,30
|
Parameters |
κ=15 |
||||||||||||
|
Source side |
Both sides |
Drain side |
|||||||||||
|
4:1 |
1:4 |
3:2 |
2:3 |
4:1 |
1:4 |
3:2 |
2:3 |
4:1 |
1:4 |
3:2 |
2:3 |
||
|
IOFF(A) |
1.62e-13 |
1.09e-13 |
9.76e-14 |
9.78e-14 |
1.53e-13 |
9.70e-14 |
1.21e-13 |
1.21e-13 |
2.75e-13 |
2.96e-13 |
1.38e-13 |
1.58e-13 |
|
|
ION(A) |
8.24e-06 |
9.29e-06 |
9.01e-06 |
9.22e-06 |
8.94e-06 |
6.84e-06 |
9.58e-06 |
1.02e-05 |
5.67e-06 |
6.11e-06 |
6.48e-06 |
6.01e-6 |
|
|
ION/IOFF |
5.07e07 |
8.47e07 |
0.92e07 |
0.94e08 |
5.82e07 |
0.70e08 |
7.88e07 |
0.84e08 |
2.06e07 |
2.05e07 |
4.80e07 |
3.79e07 |
|
|
DIBL(mV/V) |
151 |
146 |
146 |
144 |
150 |
154 |
148 |
148 |
162 |
175 |
160 |
160 |
|
|
SS(mV/dec) |
76 |
75 |
74 |
75 |
76 |
75 |
75 |
75 |
77 |
78 |
76 |
76 |
|
|
gm(S) |
1.95e-05 |
2.22e-05 |
2.17e-05 |
2.22e-05 |
2.12e-05 |
1.64e-05 |
2.32e-05 |
2.45e-05 |
1.25e-05 |
1.34e-05 |
1.47e-05 |
1.37e-05 |
|
|
TGF(V-1) |
26.19 |
26.51 |
26.66 |
26.58 |
26.44 |
26.38 |
26.56 |
26.52 |
25.94 |
25.81 |
26.46 |
26.36 |
|
|
gd(S) |
2.26e-05 |
2.96e-05 |
2.71e-5 |
2.94e-05 |
2.42e-05 |
2.81e-05 |
2.66e-05 |
2.67e-05 |
1.66e-05 |
1.42e-05 |
1.43e-05 |
1.48e-05 |
|
|
Vea(V) |
2.74 |
2.51 |
2.63 |
2.51 |
2.67 |
2.60 |
2.72 |
2.70 |
2.74 |
2.93 |
3.07 |
2.99 |
|
|
Av(dB) |
42.03 |
41.72 |
42.22 |
41.62 |
42.63 |
42.38 |
43.17 |
43.54 |
40.65 |
41.92 |
43.67 |
42.99 |
|
|
κ=22.3 |
|||||||||||||
|
IOFF(A) |
3.99e-13 |
8.91e-14 |
7.95e-14 |
7.96e-14 |
1.29e-13 |
5.81e-14 |
6.63e-14 |
1.20e-13 |
1.95e-13 |
4.82e-14 |
3.30e-14 |
4.21e-14 |
|
|
ION(A) |
7.11e-06 |
9.57e-06 |
9.27e-06 |
9.50e-06 |
8.46e-06 |
2.75e-06 |
9.88e-06 |
1.01e-05 |
9.79e-06 |
5.0e-06 |
4.15e-06 |
4.93e-06 |
|
|
ION/IOFF |
1.78e07 |
1.07e08 |
1.16e08 |
1.19e08 |
6.54e07 |
0.47e08 |
1.48e08 |
0.83e08 |
5.01e07 |
1.03e08 |
1.25e08 |
1.17e08 |
|
|
DIBL(mV/V) |
150 |
146 |
145 |
144 |
148 |
146 |
142 |
142 |
98 |
160 |
160 |
158 |
|
|
SS(mV/dec) |
79 |
75 |
73 |
74 |
76 |
74 |
73 |
75 |
75 |
73 |
72 |
72 |
|
|
gm(S) |
1.62e-05 |
2.33e-05 |
2.27e-05 |
2.32e-05 |
2.09e-05 |
1.83e-05 |
2.45e-05 |
2.45e-05 |
2.38e-05 |
1.13e-05 |
9.81e-06 |
1.13e-05 |
|
|
TGF(V-1) |
25.34 |
26.77 |
27.01 |
26.90 |
26.43 |
26.87 |
27.05 |
26.82 |
26.48 |
27.76 |
28.11 |
27.98 |
|
|
gd(S) |
2.75e-05 |
2.71e-05 |
2.57e-05 |
2.69e-05 |
2.14e-05 |
2.66e-05 |
2.44e-05 |
2.97e-05 |
1.88e-05 |
9.10e-06 |
7.99e-06 |
8.92e-06 |
|
|
Vea(V) |
2.35 |
2.72 |
2.75 |
2.72 |
2.89 |
2.72 |
2.86 |
2.72 |
2.57 |
3.11 |
2.95 |
2.98 |
|
|
Av(dB) |
38.00 |
43.57 |
43.52 |
43.47 |
43.13 |
43.85 |
44.29 |
43.51 |
20.62 |
43.49 |
43.09 |
43.31 |
|
|
κ=30 |
|||||||||||||
|
IOFF(A) |
9.41e-14 |
6.64e-14 |
5.95e-14 |
5.97e-14 |
1.06e-13 |
6.01e-14 |
1.06e-13 |
7.56e-14 |
3.29e-13 |
2.64e-13 |
1.23e-13 |
1.59e-13 |
|
|
ION(A) |
8.74e-06 |
9.94e-06 |
9.62e-06 |
9.87e-06 |
9.81e-06 |
8.02e-06 |
6.42e-06 |
1.22e-05 |
5.79e-06 |
6.45e-06 |
6.82e-06 |
6.22e-06 |
|
|
ION/IOFF |
0.92e08 |
1.49e08 |
1.61e08 |
1.65e08 |
9.20e07 |
1.33e08 |
6.03e07 |
0.14e09 |
1.75e07 |
2.44e07 |
5.54e07 |
0.39e07 |
|
|
DIBL(mV/V) |
148 |
142 |
142 |
140 |
146 |
148 |
154 |
144 |
164 |
164 |
158 |
160 |
|
|
SS(mV/dec) |
75 |
73 |
73 |
73 |
75 |
74 |
75 |
74 |
78 |
78 |
76 |
77 |
|
|
gm(S) |
2.15e-05 |
2.46e-05 |
2.40e-05 |
2.45e-05 |
2.41e-05 |
2.03e-05 |
1.54e-05 |
2.87e-05 |
1.27e-05 |
1.43e-05 |
1.57e-05 |
1.45e-05 |
|
|
TGF(V-1) |
26.69 |
27.06 |
27.19 |
27.13 |
26.46 |
26.74 |
26.87 |
26.93 |
26.77 |
27.32 |
27.46 |
26.24 |
|
|
gd(S) |
2.05e-05 |
2.59e-05 |
2.46e-05 |
2.57e-05 |
2.59e-05 |
2.36e-05 |
1.34e-05 |
2.26e-05 |
1.69e-05 |
1.36e-06 |
1.38e-06 |
1.46e-05 |
|
|
Vea(V) |
2.95 |
2.81 |
2.84 |
2.81 |
2.84 |
3.00 |
3.28 |
3.09 |
2.72 |
3.04 |
3.18 |
3.05 |
|
|
Av(dB) |
44.10 |
44.57 |
44.32 |
44.46 |
44.47 |
45.76 |
56.73 |
46.16 |
40.04 |
42.48 |
44.13 |
43.11 |
|
Case II. When Lext=2×Lg
Variation in dielectric value of high-κ in dual-κ spacers, placement of dual-κ spacers (source side, both-sides and drain side) and proportion of low and high-κ materials (4:1, 1:4, 3:2 and 2:3) has been implemented taking spacer extension length twice the gate length i.e. 30 nm. For all the cases, simulations have been done and various short channel effects and analog parameters are obtained.
(a) Effect of variation in spacer placement
Out of three cases, dual-κ (both-sides) structure has better performance parameters like ION, IOFF, ION/ IOFF, SS, gm, TGF, and Av than the other two designed devices for Lext = 2 × Lg due to longer effective gate length (Leff) as shown in Fig. 9 and 10. Performance parameters of Spacer placement along source and drain sides are also shown in Fig. 7, 8 and 11, 12 respectively.
(b) Effect of variation in proportion of dual-κ spacers
Simulated results shows that the 2:3 ratio of dual-κ spacers has minimum IOFF of 8.96 ×10-15 A, maximum ION/IOFF of order 109 and minimum SS of 67.5 mV/dec for lower dielectric value of high-κ material i.e. κ =15 with dual-κ spacers on both-sides.
(c) Effect of variation in high dielectric material
For Lext = 2 × Lg, improved parameters like IOFF, ION/IOFF were obtained with dual-κ spacer placement on both sides for κ =15 as shown in Fig. 9(a). High gain of 50.21 dB is achieved for 2:3 proportion as demonstrated in Fig. 10(b). Moreover, 112 mV/V value for DIBL is acquired for this ratio with improvement in parameters like early voltage, TGF and higher on-off current ratio than dual-κ (source) and dual-κ (drain) sides.
In this work, the influence of spacer engineering in junctionless transistor has been analyzed. The proposed device was designed and simulated using Cogenda TCAD tool at 15 nm gate length. Through this work, effect of varying spacer extension length, placement of dual-κ spacers, proportion of dual-κ spacers and dielectric value of high-κ has been studied. Simulated results shows that due longer effective gate channel length, dual-κ (both-sides) structure has minimum short channel effects and its other parameters were enhanced from the other two structures. However, dual-κ spacer placement on drain side minimizes the fringing field effect on drain side and this resulted in DIBL of 98 mV/V, Vea of 4.02 V and gd of 9.78 × 10-6 S. As the proportion of high-κ spacer increases, on-off current ratio and intrinsic gain increase as well as DIBL decrease. For short spacer extension length i.e. 1.5 times gate length, as the dielectric value of high-κ was increased, the short channel effects gets reduced and better performance parameters like ION, DIBL and Av were obtained. For longer spacer extension length (twice the gate length), improvement in device characteristics such as IOFF of 8.96× 10-15 A, ION/IOFF ratio of 0.67× 109, SS of 67.5 mV/dec, TGF of 30.12 V-1 was observed for low value of high-κ dielectric. Therefore, to get the optimum parameters of the device, a trade-off is required for low leakage applications.
This work can be extended by implementing and analyzing the concept of spacer engineering in rectzoidal fin shaped transistors [23] which proved to be effective in controlling short channel effects and providing better analog performance at nanoscale.
Acknowledgements: The authors would like to acknowledge MHRD, Govt. of India for TEQIP-II grant provided to Guru Nanak Dev Engineering College (GNDEC), Ludhiana, out of which the software was procured and the proposed work carried out. The authors are highly grateful to Principal, GNDEC, Ludhiana for the facility support in accomplishing this research work.
Funding Statement: Funding has not been availed for this work.
Availability of Data and Material: Results have been extracted by work done on TCAD tool.
Author Contributions: All authors contributed in the preparation of final manuscript.
Consent to Participate: All the authors give consent to submit paper in this journal.
Consent for Publication: The authors have agreed for submitting this manuscript in Silicon Journal and agree to publish, if accepted. It has not been sent elsewhere for consideration.
Conflicts of Interest: Authors does not have any conflicts of interest.
Ethics approval: This work complies with the ethical standards.
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