The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (LG). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (LSD), source side spacer length (LS) and drain side spacer length (LD). The simulation results give highest ION/IOFF ratio with LD variation compared to LS and LSD, whereas latter two variations have similar effect on ION/IOFF ratio. At 25 nm (2.5 × LG) of LD, the device gives appreciable ON current with the highest ION/IOFF ratio (2.19 × 108) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of LS and LD, the device ION/IOFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.
Research Article
Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching
https://doi.org/10.21203/rs.3.rs-954572/v1
This work is licensed under a CC BY 4.0 License
Journal Publication
published 04 Mar, 2022
You are reading this latest preprint version
Junctionless
GAA nanowire FET
Spacer length
ION/IOFF
SS.
Increased growth in semiconductor market improved the transistor performance but with the impact od SCEs. Various attempts to overcome the SCE problem have resulted in radical changes in transistor structural design. Many researchers predict that the vertically stacked nanowire (VS-NW) structure, is future option to drive electronic industry, which has good gate controllability and great packing density, will be the eventual destination of the shrinking transistor. The VS superior NW performance is due to its gate-all-around (GAA) based architecture. Recent research [1–3] has shown that VS-NWs are capable of balancing outstanding low off-state and high on-state properties. However, none of these studies have taken into account the VS-NW structure's spacer optimization, which is an unavoidable for sub-10 nm nodes for better gate controllability [4]. Moreover, to increase device efficiency at sub-10 nm regime JL devices are formed. Simple manufacturing method, Junction free nature, low thermal budgets, doping concentration gradient, improved scalability, and immunity to short channel effects (SCEs) are all advantages of JL based devices. [5–8].
Moreover, the JL devices exhibits better IOFF characteristics due to volume depletion nature. For volume depletion in JL FETs the need of channel thickness less than 10 nm is fundamental and advanced architectures like trigate, double gate, Gate all Around (GAA) structure is essential. Moreover, higher gate work function is also required for full depletion [9, 10]. Since JL device use volume conduction phenomena hence improves carrier transit speed and minimize surface roughness through scattering [11].
To minimize SCEs for sub-20 nm device’s, the introduction of spacers is fundamental [4]. The addition of spacers, on the other hand, enhances series resistance and so minimizes drive current (ION) current performance. The flow of gate-source/drain carriers is restricted as the spacer length increases, even at high VDS. High-k spacers increase switching ratios (ION/IOFF) by inducing field coupling via the fringing effect [12]. However, in order to achieve superior performance metrics, spacer length should be carefully chosen. Aside from thickness and width, spacer length is also carefully adjusted to improve transistor performance. According to research [13], the effect of drain asymmetry variation reduces leakages by 57 %. The inclusion of spacer reduces leakages mostly due to edge tunnelling of carriers. This paper explores symmetric and asymmetric spacer length variation on GAA NW FET at nano regime. Various performance metrics like ION, IOFF, ION/IOFF, and SS are analyzed.
The paper is organized as follows. The section 2 describes device physics and device geometrical parameters. In section 3.1 symmetrical dielectric variation of spacer length optimization is performed on SS and ION/IOFF. In section 3.2 source spacer length is varied (LS) by keeping drain spacer length (LD) constant. In section 3.3 drain spacer length is varied (LD) by keeping LS as constant. Section 4 illustrates the CMOS inverter performance of symmetric and asymmetric spacers.
Figure 1 depicts the 3-D JL SOI nanowire FET and 2-D view of symmetric spacer. In this paper we have considered 3-D JL SOI VS NW FET to understand the effect of spacer length on device DC performance. The high-k dielectric HfO2 is used as a spacer material to increase switching performance. Although the use of spacer length improves subthreshold performance, but reduces ON current. As a result, a spacer length with a high-k dielectric is provided to compensate for this impact, increasing ON current by increasing electron flow from source to drain. Furthermore, introducing high-k gate dielectric along with interfacial oxide (SiO2) achieves a lower EOT and better gate electrostatics, the suppression of leakages, and the suppression of random threshold voltage changes [14, 15]. The OFF current is maintained <100 pA for all variations with a fixed work function of 4.8 eV. With Titanium (Ti) as the gate metal, continuous and uniform doping is maintained.
Higher channel doping concentrations activate Fermi Dirac statistics. Since carrier degradation phenomena are produced by surface roughness, acoustic phonon scattering, and doping dependency mobility reduction, the Lombardi mobility model is taken into account. A band-to-band tunnelling model is included to handle the band gap narrowing effect that can occur as a result of increased channel doping. To account for carrier production and recombination events, the Shockley-Read-Hall (SRH) model is used. To account for quantum correction effects, quantum models are used. The threshold voltage is extracted at (W/L) × 10 -7 A at VDS = 0.9 V and VGS = 1.2 V. The simulation models have been thoroughly calibrated using experimental data [17]. The simulations are carried out through 3D Cogenda Visual TCAD simulator [16].
3.1 Symmetric variation of Spacer Length
Fig 2 depicts the ON-OFF parameters and subthreshold characteristics received from the TCAD simulator are examined. The VS NW FET demonstrates behavioral change with modification in spacer length, as shown in Fig. 2(a) and (b), with both ION and IOFF decreasing as spacer length increases. Longer spacers produce good subthreshold behavior but result in a decrease in ON current due to the increased series resistance. Due to downfall in edge tunnelling from source to drain and gate overlap results in lowering of IOFF with more spacer distance i.e., higher LSD/LG ratio.
From Fig. 3 it is observed that the symmetric spacer exhibits highest ION/IOFF of 2.65 × 108 and lower SS of 63 mV/dec at LSD = 1.5 × LG. Moreover, the device exhibits diminished ION/IOFF at LSD = 2 × LG and thus removed from design of symmetric spacer perspective.
3.2 LS variation with fixed LD
The length of the spacer dielectric is asymmetrically altered in this section. The source side spacer length is adjusted while the drain spacer length is kept constant at 1.5 × LG, because the device achieves the maximum ION/IOFF ratio and mild SS at this symmetric spacer length. From the Fig.4(a) and (b) increase in LS length the ON current decreases at fixed LD length of 15 nm. From the Fig.5 the ION/IOFF ratio increases with raise in LS/LG value and reaches to highest value at 1.5 × LG.
Fig 5 depicts the asymmetric spacer variation of LS in ON state. The device exhibits highest ION/IOFF ratio at LS = 1.5 × LG. The ION/IOFF of 2.6 × 108 is obtained at source spacer length optimization which is permissible for driving logic applications. However, the device exhibits down fall after LS = 1.5 × LG due to increase of OFF state electron tunneling with more LS.
3.3 LD variation with fixed LS
In this section, the same analysis as in section 3.2 is carried out, but the drain side spacer length is altered while the source side spacer length is fixed at 1.5 × LG. The greater the LD/LG, the lower the IOFF and the lower the ION, as shown in Fig. 6(a) and (b). The ION increases with lower LD length. Since higher LD of device leads to higher resistance to electron flow. Moreover, the IOFF which is significant for low stand by power applications is reduced with higher LD/LG value. Since in OFF state the spacer dielectric fringing fields increase the potential barrier height and restrict tunneling of electrons.
From Fig.7, increase in spacer length the ION/IOFF ratio increases up to 2.5 × LG and then degrades. The device achieves the highest ION/IOFF ratio at LS = 15 nm and LD = 25 nm at LG = 10 nm with acceptable SS. Moreover, the device ION/IOFF ratio falls after 2.5 × LG due to reduced fringing effect with larger LD. Thus, spacer optimization is vital for enhanced performance at nano regime.
3.4. Comparisonof source/drain sidespacerlengthvariation
The performance metrics of LS and LD variation on ION, IOFF, ION/IOFF, and SS are compared in this section and displayed in Figs. 8 and 9. Both LS and LD variation on VS NW FET shows contrasting effect on performance metrics. From Fig.8(a) and (b), both ON current and OFF current decreases with increase in LS and LD. The ON current of LS is higher compared to LD up to 1 × LG, whereas opposite behavior results from 1.5 × LG to 2.5 × LG.
The OFF current of LS is more compared to LD with spacer distance variation. The lowest OFF current for LS and LD takes place at highest spacer length i.e., at 2.5 × LG whereas, the highest OFF current occurs at lowest spacer distance i.e., 0.2 × LG. Since the highest OFF current occurs at 0.2 × LG, 0.5 × LG and hence they are discarded for device design prospective. The permissible LS and LD values for device design are 1 × LG, 1.5 × LG, 2 × LG, and 2.5 × LG respectively. However, the best optimized device set is at LS = 1.5 × LG and LD = 2.5 × LG with acceptable SS.
Figure 9(a) and (b) shows the ION/IOFF and SS performance of the VS NW FET with both LS and LD versions. The ION/IOFF ratio diminishes after 2 × LG for LS whereas it increases up to 1.5 × LG for both LS and LD spacer length variations, whereas the ratio degrades. So, the maximum allowable range of LS variation is are limited to LS = 1.5 × LG to drive device for better switching and low power applications.
Figure 9(a) shows the SS performance of the VS NW FET for both LS and LD variations, with the highest SS value at 0.2 × LG and the lowest value at 2.5 × LG. Except at 0.2 × LG, the device achieves the lowest SS among LS, LD variations.
The Figure 9(a) and (b) show the ID-VGS characteristics with symmetric (LS = 15 nm and LD = 15 nm) and asymmetric (LS = 15 nm and LD = 25 nm) combinations.
The simulated transfer characteristics (ID-VGS) with different spacer dielctrics of JL nanowire FET with symmetric spacer are shown in Figure 10(a). With all spacer dielectrics, the device has an IOFF of less than nA. With spacer dielectrics, however, the ION varies from 60 to 75 A. The ID-VGS of asymmetric spacer variation follow the same pattern as symmetric variation, as shown in Fig. 10(b). For all spacer combinations, the IOFF of the device with asymmetric spacer is less than nA. With the HfO2 spacer, the ION reaches a maximum of 68 A, while with no spacer, it reaches 54 A. According to the results, a rise in the ‘k' value causes a decrease in IOFF. Stronger fringing fields result in lower IOFF when the ‘k' value is higher. Due to the spacer fringing electric fields, the depletion region improves. The p-n junctions form the depletion zone in inversion mode FETs, whereas energy barrier generation owing to depletion in the OFF state occurs in JL devices. The subthreshold current decreases as the spacer dielectric value increases because of high vertical electric field at VDS = 0.9 V and VGS = 0 V i.e., in the OFF state. Furthermore, the ID is marginally affected in the ON state due to the zero electric field induced by the flat band situation. In comparison to Air and SiO2 spacers, the HfO2 followed by Si3N4 spacer has good switching behavior and a lower IOFF at nano-regime. As a consequence of the analysis, high-k spacer dielectrics such as Si3N4 and HfO2 excel with better subthreshold and switching behavior at nano-regime, ensuring potential candidate for low-power applications [17].
The ION for a device is calculated at VDS = 0.9 V and VGS = 1.2 V whereas, IOFF is calculated at VDS = 0.9 V and VGS = 0 V. As seen in Fig. 11(a), the ION is much lower with the asymmetric spacer than with the symmetric spacer. HfO2 has the smallest ION decrease of all the spacer combinations, at 11.24%. The Si3N4 spacer and no spacer materials had a 13.26 percent and 15.8 percent drop, respectively. Because higher fringing fields with a high-k spacer diminish the ION decrement with asymmetric spacer compared to a low-k spacer, the ION decrement with asymmetric spacer is minimized. The IOFF for various spacer dielectrics is shown in Figure 11(b). Although symmetric spacers improve ION, asymmetric spacers diminish direct tunnelling of electrons in the OFF state due to the greater distance between the channel and drain. The ION/IOFF ratio of a device with varied spacer dielectrics is shown in Figure 11(c). With only SiO2, Si3N4, and HfO2 spacers, the asymmetric spacer has a greater ION/IOFF ratio than the symmetric spacer. In comparison to Air and no spacer, the symmetric spacer exhibits a modest increase in the ION/IOFF ratio due to increased ION and marginal IOFF fluctuation. The negligible difference in IOFF between symmetric and asymmetric spacers for Air and no spacer is attributed to ineffective leakage control due to decreased dielectric fringing fields. Furthermore, the asymmetric spacer aims to improve the ION/IOFF ratio while lowering coupling and parasitic capacitances [18, 19]. With HfO2 spacer, the asymmetric spacer improves the ION/IOFF ratio by 19.6% and reduces IOFF by 34.13% when compared to the symmetric spacer. Furthermore, as seen in Fig. 11(d), the performance of SS is poorer with an asymmetric spacer. Although the ION is lowered by 11.24% with the asymmetric spacer, the subthreshold behavior and switching performance are improved thanks to a spectacular reduction in IOFF.
The electric field on the channel region of the symmetric spacer is higher than that of the asymmetric spacer, as shown in Fig. 12(a) and (b). Due to larger distance between the channel and drain in the asymmetric spacer the electric field lines are minimized into the silicon and thus enhanced tunnelling width. Figures 12(c) and 12(d) demonstrate the potential distribution of JL nanowire FETs with symmetric and asymmetric spacers. Because of the long distance between channel and drain, an asymmetric spacer ensures lower SCEs.
4. CMOS Inverter Performance Analysis
Figure 13 depicts the ID-VGS characteristics of both NMOS and PMOS with optimized symmetric and asymmetric spacers. The gate length LG = 10 nm, EOT (high-k+SiO2) = 0.75 nm, Si channel thickness =10 nm, and HfO2 as spacer material have all been maintained same as in NMOS. The design for PMOS symmetric spacer is LS = LD = 15 nm and LS = 15 nm and LD = 25 nm for asymmetric spacer, which is maintained same as NMOS. The Vt is matched for both NMOS and PMOS by work function engineering. The SS and DIBL of symmetric and asymmetric spacers NMOS are depicted inside Fig. 13. Furthermore, the delay performance is calculated by CMOS inverter as shown in Fig 14.
The CMOS inverter delay (TD) is calculated using the effective drive current model, such as in equation 1 [20], where IEFF is the effective drive current, CL is the load capacitance, and VDD is the supply voltage of the first stage inverter at the output node.
The evaluation of CL is carried through parasitic first stage output and input capacitance of second stage as (2) and a value of 1.5 is considered for miller coefficient (M) [21]. The CIN2 is calculated by using the weighted distribution of NMOS and PMOS during input transitions of the OFF and ON-state capacitances. During the output-fall transition to 0.5VDD, the transistor P2 remains ON while N2 switches from OFF to ON. As a result, the OFF to ON ratio of 0.25: 0.75[20-22] is utilized to calculate CIN2 (3).
Where, IEFF = (IL+ IH+ IM)/3, IM = IDS (VDS = 0.75VDD, IH = IDS (VGS = VDD, VDS = 0.5VDD), VGS = 0.75VDD) and IL = IDS (VGS = 0.5VDD, VDS = VDD,) as defined in [21], and are taken from the individual ID-VGS characteristics.
Figure15 depicts the CMOS inverter delay of symmetric and asymmetric spacer dielectrics. The terms tPHL and tPLH defines the speed of the logic and detrimental in calculating propagation delay (tP). The symmetric spacer exhibits lower delay compared to asymmetric spacers. Since in asymmetric spacer the LD is 25 nm which is higher compared to symmetric spacer which is 15 nm. Thus, symmetric spacer is better for circuit applications at nano regime. However, asymmetric spacer outperforms symmetric spacer in terms of OFF current, subthreshold performance, and good switching behavior.
In thiswork detailed study of spacer length has been presented on n-channel SOI JL VS NW FET. According to the performance optimization metrics, spacer length modification has a serious effect on SCE reduction. By result analysis the ION/IOFF ratio with LS =1.5 nm and LD = 2.5 nm exhibits best performance. Among optimized LS and LD values an improvement of 22.69 % in ION/IOFF ratio is noticed with LD = 2.5 × LG, whereas the SS is reduced i.e., 63 mV/dec to 62 mV/dec. The highest OFF current with 0.2 × LG and 0.5 × LG for both LS and LD variations are not considered for device design considerations. For LS variations 2 × LG and 2.5 × LG are neglected, whereas for LD the spacer length 3 × LG is not considered since the device ION/IOFF ratio tends to down fall. From the result analysis with LS = 15 nm LD = 25 nm and high-k spacer for 10 nm n-channel JL VS NW FET shows best optimized results. Hence optimized asymmetric VS NW FET exhibit low OFF current, higher ION/IOFF ratio and hence assures low standby power requirements and low power applications. Moreover, symmetric spacer exhibits higher ION and lower delay and assures high performance applications.
Author Contributions
V. Bharath Sreenivasulu: Writing- Original draft preparation, Formal Analysis, Investigation, Simulation, Data Curation.
V. Narendar: Supervision, Resources.
Financial interests: The authors declare they have no financial interests.
Funding: No Funding Received.
Conflict of Interest: The author has no conflicts of interest to declare that are relevant to the content of this article.
Compliance with Ethical Standards:
- The contents of this manuscript are not now under consideration for publication elsewhere;
- The contents of this manuscript have not been copyrighted or published previously
- The contents of this manuscript will not be copyrighted, submitted, or published elsewhere, while acceptance by the Journal is under consideration.
Availability of data and material: Not applicable.
Consent to Participate: Not applicable.
Consent for Publication: Not applicable.
Acknowledgements: The authors thank to the department of Electronics and Communications Engineering, NIT Warangal for providing the TCAD Tools.
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